On 20 December 2013 22:16, Peter Maydell wrote:
> More generally I think the way that AArch64 uses op1 to group
> the registers by exception-level-access-rights is going to make it
> a bit tricky to do the mapping; we either need to
> (1) have .opc1 be the AA32 opc1 and infer AA64 op1 from
> the p
On 20 December 2013 22:29, Peter Crosthwaite
wrote:
> On Sat, Dec 21, 2013 at 8:07 AM, Peter Maydell
> wrote:
>> On 20 December 2013 21:41, Peter Crosthwaite
>> wrote:
>>> So to clarify, would MIDR and friends be in this bucket? And does t
>>> obsolete the old MIDR def such there is only one CP
On Sat, Dec 21, 2013 at 8:07 AM, Peter Maydell wrote:
> On 20 December 2013 21:41, Peter Crosthwaite
> wrote:
>> On Sat, Dec 21, 2013 at 4:16 AM, Peter Maydell
>> wrote:
>>> On 20 December 2013 10:00, Peter Maydell wrote:
I'll have a think about this, because there are some wrinkles relat
On 20 December 2013 22:07, Peter Maydell wrote:
> On 20 December 2013 21:41, Peter Crosthwaite
> wrote:
>> On Sat, Dec 21, 2013 at 4:16 AM, Peter Maydell
>> wrote:
>>> * for the few registers which aren't neatly arranged so the
>>>crn/crm/opc1/opc2 line up, we just split up into a separate
On 20 December 2013 21:41, Peter Crosthwaite
wrote:
> On Sat, Dec 21, 2013 at 4:16 AM, Peter Maydell
> wrote:
>> On 20 December 2013 10:00, Peter Maydell wrote:
>>> I'll have a think about this, because there are some wrinkles relating
>>> to reset that might be usefully solved this way.
>>
>>
On Sat, Dec 21, 2013 at 4:16 AM, Peter Maydell wrote:
> On 20 December 2013 10:00, Peter Maydell wrote:
>> I'll have a think about this, because there are some wrinkles relating
>> to reset that might be usefully solved this way.
>
> So my conclusion here is that really this boils down to how we
On Fri, Dec 20, 2013 at 04:43:23PM +, Peter Maydell wrote:
> On 17 December 2013 15:12, Peter Maydell wrote:
> > +MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP0_MASK, KVM_REG_ARM64_SYSREG_OP0_MASK)
> > +MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP0_SHIFT,
> > KVM_REG_ARM64_SYREG_OP0_SHIFT)
> > +MISMATCH_CHE
On 20 December 2013 10:00, Peter Maydell wrote:
> I'll have a think about this, because there are some wrinkles relating
> to reset that might be usefully solved this way.
So my conclusion here is that really this boils down to how we
want to deal with sysregs for AArch64 capable CPUs in general.
On 20 December 2013 04:24, Peter Crosthwaite
wrote:
> On Thu, Dec 19, 2013 at 7:11 PM, Peter Maydell
> wrote:
>> On 19 December 2013 06:01, Peter Crosthwaite
>> wrote:
>>> On Wed, Dec 18, 2013 at 1:12 AM, Peter Maydell
>>> wrote:
+*key = ENCODE_AA64_CP_REG(r2->cp, r->
On 17 December 2013 15:12, Peter Maydell wrote:
> +MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP0_MASK, KVM_REG_ARM64_SYSREG_OP0_MASK)
> +MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP0_SHIFT, KVM_REG_ARM64_SYREG_OP0_SHIFT)
> +MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP1_MASK, KVM_REG_ARM64_SYSREG_OP1_MASK)
> +MISMATCH_
On 20 December 2013 04:24, Peter Crosthwaite
wrote:
> On Thu, Dec 19, 2013 at 7:11 PM, Peter Maydell
> wrote:
>> Almost all the shared registers appear as 32 bit on the AArch32
>> side and 64 bits on the AArch64 side.
>
> Really? Reading v8, there are many 32 bit regs with these op0 AArch64
> en
On Wed, Dec 18, 2013 at 1:12 AM, Peter Maydell wrote:
> Update the generic cpreg support code to also handle AArch64:
> AArch64-visible registers coexist in the same hash table with
> AArch32-visible ones, with a bit in the hash key distinguishing
> them.
>
> Signed-off-by: Peter Maydell
> ---
>
On Thu, Dec 19, 2013 at 7:11 PM, Peter Maydell wrote:
> On 19 December 2013 06:01, Peter Crosthwaite
> wrote:
>> On Wed, Dec 18, 2013 at 1:12 AM, Peter Maydell
>> wrote:
>>> +*key = ENCODE_AA64_CP_REG(r2->cp, r->crn, crm,
>>> + r-
On 19 December 2013 06:01, Peter Crosthwaite
wrote:
> On Wed, Dec 18, 2013 at 1:12 AM, Peter Maydell
> wrote:
>> +*key = ENCODE_AA64_CP_REG(r2->cp, r->crn, crm,
>> + r->opc0, opc1, opc2);
>
> You have mixed terminology here with "o
On Wed, Dec 18, 2013 at 1:12 AM, Peter Maydell wrote:
> Update the generic cpreg support code to also handle AArch64:
> AArch64-visible registers coexist in the same hash table with
> AArch32-visible ones, with a bit in the hash key distinguishing
> them.
>
> Signed-off-by: Peter Maydell
> ---
>
Update the generic cpreg support code to also handle AArch64:
AArch64-visible registers coexist in the same hash table with
AArch32-visible ones, with a bit in the hash key distinguishing
them.
Signed-off-by: Peter Maydell
---
target-arm/cpu.h| 59 ++--
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