On 28 May 2015 at 14:27, Edgar E. Iglesias wrote:
> Thanks for clarifying that. With the !arm_is_secure_below_el3(env)
> change:
>
> Reviewed-by: Edgar E. Iglesias
Thanks. Since there have only been a few trivial fixups I've applied
the series to target-arm.next.
-- PMM
On Thu, May 28, 2015 at 02:19:42PM +0100, Peter Maydell wrote:
> On 28 May 2015 at 13:50, Edgar E. Iglesias wrote:
> > On Tue, May 19, 2015 at 07:33:31PM +0100, Peter Maydell wrote:
> >> +/* For the CPTR registers we don't need to guard with an ARM_FEATURE
> >> + * check because zero bits
On 28 May 2015 at 13:50, Edgar E. Iglesias wrote:
> On Tue, May 19, 2015 at 07:33:31PM +0100, Peter Maydell wrote:
>> +/* For the CPTR registers we don't need to guard with an ARM_FEATURE
>> + * check because zero bits in the registers mean "don't trap".
>> + */
>> +
>> +/* CPTR_EL
On Tue, May 19, 2015 at 07:33:31PM +0100, Peter Maydell wrote:
> From: Greg Bellows
>
> Extend the ARM disassemble context to take a target exception EL instead of a
> boolean enable. This change reverses the polarity of the check making a value
> of 0 indicate floating point enabled (no exceptio
From: Greg Bellows
Extend the ARM disassemble context to take a target exception EL instead of a
boolean enable. This change reverses the polarity of the check making a value
of 0 indicate floating point enabled (no exception).
Signed-off-by: Greg Bellows
[PMM: Use a common TB flag field for AA
