On 10 October 2012 11:00, Laurent Desnogues wrote:
> On Tue, Oct 9, 2012 at 11:13 PM, Peter Maydell
> wrote:
>> On 9 October 2012 21:30, Aurelien Jarno wrote:
>>> +if (im >= 0) {
>>> +tcg_out32(s, (cond << 28) | 0x05b0 |
>>> + (rn << 16) | (rd << 12) | (im
On Tue, Oct 9, 2012 at 11:13 PM, Peter Maydell wrote:
> On 9 October 2012 21:30, Aurelien Jarno wrote:
>> The TCG arm backend considers likely that the offset to the TLB
>> entries does not exceed 12 bits for mem_index = 0. In practice this is
>> not true for at list the MIPS target.
>>
>> The cu
The TCG arm backend considers likely that the offset to the TLB
entries does not exceed 12 bits for mem_index = 0. In practice this is
not true for at list the MIPS target.
The current patch fixes that by loading the bits 23-12 with a separate
instruction, and using loads with address writeback, i
On 9 October 2012 21:30, Aurelien Jarno wrote:
> The TCG arm backend considers likely that the offset to the TLB
> entries does not exceed 12 bits for mem_index = 0. In practice this is
> not true for at list the MIPS target.
>
> The current patch fixes that by loading the bits 23-12 with a separa
