On Sun, Mar 17, 2019 at 1:24 AM Bin Meng wrote:
>
> At present the sifive uart model only generates RX interrupt. This
> updates it to generate TX interrupt so that it is more useful.
>
> Note the TX fifo is still unimplemented.
>
> Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Alistai
At present the sifive uart model only generates RX interrupt. This
updates it to generate TX interrupt so that it is more useful.
Note the TX fifo is still unimplemented.
Signed-off-by: Bin Meng
---
hw/riscv/sifive_uart.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/h
