On 07/07/2014 11:13 AM, Bastian Koppelmann wrote:
> +case OPC1_16_SSR_ST_B:
> +r1 = MASK_OP_SSR_S1(ctx->opcode);
> +r2 = MASK_OP_SSR_S2(ctx->opcode);
> +temp = tcg_temp_new();
> +tcg_gen_andi_tl(temp, cpu_gpr_d[r1], 0xff);
> +tcg_gen_qemu_st8(temp, cpu_gp
Add instructions of SSR opcode format.
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 57 ++
1 file changed, 57 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 108619c..7553870 100644
--- a/
