Re: [Qemu-devel] [PATCH 08/10] target-mips: Fix check_cp1_64bitmode

2013-03-05 Thread Aurelien Jarno
On Sun, Feb 10, 2013 at 10:30:48AM -0800, Richard Henderson wrote: > COP1X refers to the availability of indexed memory operations, > not whether the FPU has 64-bit registers. > > Signed-off-by: Richard Henderson > --- > target-mips/translate.c | 3 ++- > 1 file changed, 2 insertions(+), 1 delet

[Qemu-devel] [PATCH 08/10] target-mips: Fix check_cp1_64bitmode

2013-02-10 Thread Richard Henderson
COP1X refers to the availability of indexed memory operations, not whether the FPU has 64-bit registers. Signed-off-by: Richard Henderson --- target-mips/translate.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index b3b8