Re: [Qemu-devel] [PATCH 06/10] target-arm: A64: Add SIMD ZIP/UZP/TRN

2014-01-11 Thread Alex Bennée
r...@twiddle.net writes: > On 01/10/2014 09:12 AM, Peter Maydell wrote: >> +for (i = 0; i < elements; i++) { >> +switch (opcode) { >> +case 1: /* UZP1/2 */ >> +{ >> +int midpoint = elements / 2; >> +if (i < midpoint) { >> +read_v

Re: [Qemu-devel] [PATCH 06/10] target-arm: A64: Add SIMD ZIP/UZP/TRN

2014-01-10 Thread Richard Henderson
On 01/10/2014 09:12 AM, Peter Maydell wrote: > +for (i = 0; i < elements; i++) { > +switch (opcode) { > +case 1: /* UZP1/2 */ > +{ > +int midpoint = elements / 2; > +if (i < midpoint) { > +read_vec_element(s, tcg_res, rn, 2 * i + p

[Qemu-devel] [PATCH 06/10] target-arm: A64: Add SIMD ZIP/UZP/TRN

2014-01-10 Thread Peter Maydell
From: Michael Matz Add support for the SIMD ZIP/UZIP/TRN instruction group (C3.6.3). Signed-off-by: Michael Matz [PMM: use new do_vec_get/set etc functions and generally update to new codebase standards; refactor to pull per-element loop outside switch] Signed-off-by: Peter Maydell --- targe