On 18.03.2011, at 05:03, David Gibson wrote:
> On Thu, Mar 17, 2011 at 08:20:52AM -0500, Anthony Liguori wrote:
>> On 03/16/2011 11:55 PM, David Gibson wrote:
>>> On Wed, Mar 16, 2011 at 03:44:49PM -0500, Anthony Liguori wrote:
On 03/15/2011 11:56 PM, David Gibson wrote:
> [snip]
Is th
On Thu, Mar 17, 2011 at 08:20:52AM -0500, Anthony Liguori wrote:
> On 03/16/2011 11:55 PM, David Gibson wrote:
> >On Wed, Mar 16, 2011 at 03:44:49PM -0500, Anthony Liguori wrote:
> >>On 03/15/2011 11:56 PM, David Gibson wrote:
[snip]
> >>Is the hypercall handler ever specific to a CPU?
> >If you me
On 03/16/2011 11:55 PM, David Gibson wrote:
On Wed, Mar 16, 2011 at 03:44:49PM -0500, Anthony Liguori wrote:
On 03/15/2011 11:56 PM, David Gibson wrote:
From: David Gibson
PowerPC and POWER chips since the POWER4 and 970 have a special
hypervisor mode, and a corresponding form of the system ca
On Wed, Mar 16, 2011 at 03:44:49PM -0500, Anthony Liguori wrote:
> On 03/15/2011 11:56 PM, David Gibson wrote:
> >From: David Gibson
> >
> >PowerPC and POWER chips since the POWER4 and 970 have a special
> >hypervisor mode, and a corresponding form of the system call
> >instruction which traps to t
On 03/15/2011 11:56 PM, David Gibson wrote:
From: David Gibson
PowerPC and POWER chips since the POWER4 and 970 have a special
hypervisor mode, and a corresponding form of the system call
instruction which traps to the hypervisor.
qemu currently has stub implementations of hypervisor mode. Tha
From: David Gibson
PowerPC and POWER chips since the POWER4 and 970 have a special
hypervisor mode, and a corresponding form of the system call
instruction which traps to the hypervisor.
qemu currently has stub implementations of hypervisor mode. That
is, the outline is there to allow qemu to r
