On Sat, May 19, 2012 at 10:57 AM, Peter Maydell
wrote:
> On 19 May 2012 11:02, Blue Swirl wrote:
>>> +static inline uint32_t field(uint32_t val, int start, int length)
>>> +{
>>> + val >>= start;
>>> + val &= ~(~0 << length);
>>> + return val;
>>> +}
>>
>> Nice function, maybe I could us
On 19 May 2012 11:02, Blue Swirl wrote:
>> +static inline uint32_t field(uint32_t val, int start, int length)
>> +{
>> + val >>= start;
>> + val &= ~(~0 << length);
>> + return val;
>> +}
>
> Nice function, maybe I could use it in Sparc as well if generalized (later).
We should totally h
Hi Jia.
>>> + case 0x0009:
>>> + switch (op1) {
>>> + case 0x03: /*l.div*/
>>> + LOG_DIS("l.div r%d, r%d, r%d\n", rd, ra, rb);
>>> + if (rb != 0) {
>>> + tcg_gen_div_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
>>
>> You also need to take care of int
> >> + ? 坟witch (op0) {
> >> + ? ?case 0x10: ? ?/*lf.add.d*/
> >> + ? ? ? 猂OG_DIS("lf.add.d r%d, r%d, r%d\n", rd, ra, rb);
> >> + ? ? ? 慯cg_gen_add_i64(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
> >
> > Through this function you generate integer operations on the
> > registers, although ISA
> > suggests tha
Hi Max
Thanks for comments.
On Thu, May 17, 2012 at 8:11 PM, Max Filippov wrote:
> Hi.
>
> I've got a couple of questions/suggestions regarding the code.
>
> On Thu, May 17, 2012 at 12:35 PM, Jia Liu wrote:
>> add the openrisc instructions translation.
>>
>> Signed-off-by: Jia Liu
>
> [...]
>
Hi.
I've got a couple of questions/suggestions regarding the code.
On Thu, May 17, 2012 at 12:35 PM, Jia Liu wrote:
> add the openrisc instructions translation.
>
> Signed-off-by: Jia Liu
[...]
> + case 0x0009:
> + switch (op1) {
> + case 0x03: /*l.div*/
> + LOG_
add the openrisc instructions translation.
Signed-off-by: Jia Liu
---
target-openrisc/translate.c | 1387 +++
1 file changed, 1387 insertions(+)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index aae483a..4828ae6 100644
--- a/tar
