On Thu, Aug 28, 2014 at 09:35:27PM +0200, Paolo Bonzini wrote:
> Il 28/08/2014 19:30, Peter Maydell ha scritto:
> > On 28 August 2014 18:14, Paolo Bonzini
> wrote:
[snip]
> > Does PPC hardware do lots of TLB flushes on user-kernel
> > transitions, or does it have some sort of info in the TLB
> > e
Il 28/08/2014 19:30, Peter Maydell ha scritto:
> On 28 August 2014 18:14, Paolo Bonzini wrote:
>> PowerPC TCG flushes the TLB on every IR/DR change, which basically
>> means on every user<->kernel context switch. Use the 6-element
>> TLB array as a cache, where each MMU index is mapped to a diffe
On 28 August 2014 18:14, Paolo Bonzini wrote:
> PowerPC TCG flushes the TLB on every IR/DR change, which basically
> means on every user<->kernel context switch. Use the 6-element
> TLB array as a cache, where each MMU index is mapped to a different
> state of the IR/DR/PR/HV bits.
>
> This bring
PowerPC TCG flushes the TLB on every IR/DR change, which basically
means on every user<->kernel context switch. Use the 6-element
TLB array as a cache, where each MMU index is mapped to a different
state of the IR/DR/PR/HV bits.
This brings the number of TLB flushes down from ~90 to ~5
fo
