On 17.03.2011, at 00:08, Michael Walle wrote:
> Am Freitag 11 März 2011, 06:57:18 schrieben Sie:
>> On 17.02.2011, at 23:51, Michael Walle wrote:
>>> Am Samstag 12 Februar 2011, 07:49:52 schrieb Blue Swirl:
> That said, IMHO the best handling of unknown opcodes would be to kill
> the
Am Freitag 11 März 2011, 06:57:18 schrieben Sie:
> On 17.02.2011, at 23:51, Michael Walle wrote:
> > Am Samstag 12 Februar 2011, 07:49:52 schrieb Blue Swirl:
> >>> That said, IMHO the best handling of unknown opcodes would be to kill
> >>> the VM.
> >>
> >> In this case it should be OK. Alternativ
On 17.02.2011, at 23:51, Michael Walle wrote:
> Am Samstag 12 Februar 2011, 07:49:52 schrieb Blue Swirl:
>>> That said, IMHO the best handling of unknown opcodes would be to kill the
>>> VM.
>>
>> In this case it should be OK. Alternatively the VM could be halted, so
>> that instead of restartin
Am Samstag 12 Februar 2011, 07:49:52 schrieb Blue Swirl:
> > That said, IMHO the best handling of unknown opcodes would be to kill the
> > VM.
>
> In this case it should be OK. Alternatively the VM could be halted, so
> that instead of restarting QEMU, only system_reset needs to be issued.
> This
This patch adds the main translation routine. All opcodes of the
LatticeMico32 processor are supported and translated to TCG ops.
Signed-off-by: Michael Walle
---
target-lm32/helper.c | 259 +
target-lm32/lm32-decode.h | 78 +++
target-lm32/translate.c | 1317 ++
Am Freitag 11 Februar 2011, 22:42:28 schrieb Blue Swirl:
> > +/* Convenient binary macros */
> > +#define HEX__(n) 0x##n##LU
> > +#define B8__(x) (((x&0x000FLU) ? 1 : 0) \
> > + + ((x&0x00F0LU) ? 2 : 0) \
> > + + ((x&0x0F00LU) ? 4 : 0) \
> > +
On Sat, Feb 12, 2011 at 12:23 AM, Michael Walle wrote:
> Hi,
>
> Regarding all the comments on raising an exception. The real hardware does
> only support a few basic exception (like div by zero or interrupts and system
> calls). There is no checking if an instruction is supported or not. If an
>
Hi,
Regarding all the comments on raising an exception. The real hardware does
only support a few basic exception (like div by zero or interrupts and system
calls). There is no checking if an instruction is supported or not. If an
illegal opcode (like divu if the hardware divider is not enabled
This patch adds the main translation routine. All opcodes of the
LatticeMico32 processor are supported and translated to TCG ops.
Signed-off-by: Michael Walle
---
target-lm32/helper.c | 259 +
target-lm32/lm32-decode.h | 78 +++
target-lm32/translate.c | 1315 ++
Am Dienstag 08 Februar 2011, 18:32:57 schrieb Richard Henderson:
> On 01/30/2011 04:30 PM, Michael Walle wrote:
> > +if (dc->format == OP_FMT_RI) {
> > +tcg_gen_brcondi_tl(cond, cpu_R[rY], sign_extend(dc->imm16, 16),
> > l1); +} else {
> > +tcg_gen_brcond_tl(cond, cpu_R[rY],
On Tue, Feb 08, 2011 at 09:32:57AM -0800, Richard Henderson wrote:
> On 01/30/2011 04:30 PM, Michael Walle wrote:
> > +if (dc->format == OP_FMT_RI) {
> > +tcg_gen_brcondi_tl(cond, cpu_R[rY], sign_extend(dc->imm16, 16),
> > l1);
> > +} else {
> > +tcg_gen_brcond_tl(cond, cpu
On 01/30/2011 04:30 PM, Michael Walle wrote:
> +if (dc->format == OP_FMT_RI) {
> +tcg_gen_brcondi_tl(cond, cpu_R[rY], sign_extend(dc->imm16, 16), l1);
> +} else {
> +tcg_gen_brcond_tl(cond, cpu_R[rY], cpu_R[rZ], l1);
> +}
> +tcg_gen_movi_tl(cpu_R[rX], 0);
> +tcg_
This patch adds the main translation routine. All opcodes of the
LatticeMico32 processor are supported and translated to TCG ops.
Signed-off-by: Michael Walle
---
target-lm32/helper.c | 259 +
target-lm32/lm32-decode.h | 78 +++
target-lm32/translate.c | 1331 ++
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