Re: [Qemu-devel] [PATCH 00/21] Sparc FPU/VIS improvements

2011-10-18 Thread Blue Swirl
On Tue, Oct 18, 2011 at 8:03 PM, Richard Henderson wrote: > On 10/18/2011 12:50 PM, Blue Swirl wrote: >> Thanks. Unfortunately I'm not sure I'll be able to fix and push my >> series before the freeze, because other than x86_64, none of the TCG >> targets implement AREG0 free mode. > > Oh, I see, y

Re: [Qemu-devel] [PATCH 00/21] Sparc FPU/VIS improvements

2011-10-18 Thread Richard Henderson
On 10/18/2011 12:50 PM, Blue Swirl wrote: > Thanks. Unfortunately I'm not sure I'll be able to fix and push my > series before the freeze, because other than x86_64, none of the TCG > targets implement AREG0 free mode. Oh, I see, you've not actually left the "normal" load/store helpers in op_helpe

Re: [Qemu-devel] [PATCH 00/21] Sparc FPU/VIS improvements

2011-10-18 Thread Blue Swirl
On Tue, Oct 18, 2011 at 6:50 PM, Richard Henderson wrote: > This started out to be simply flushing out the VIS2 instruction set. > But when I got a look a the DT0/1 "calling convention" I choked, and > thought we could really do better than that. > > The end result (op_opt,out_asm) looks significa

[Qemu-devel] [PATCH 00/21] Sparc FPU/VIS improvements

2011-10-18 Thread Richard Henderson
This started out to be simply flushing out the VIS2 instruction set. But when I got a look a the DT0/1 "calling convention" I choked, and thought we could really do better than that. The end result (op_opt,out_asm) looks significantly cleaner for a 64-bit host. It looks about the same for a 32-bi