Thanks, applied all.
On Wed, Dec 5, 2012 at 3:15 AM, Max Filippov wrote:
> Hi.
>
> This is my current patch queue for xtensa:
> - add support for a number of Special Registers: ATOMCTL, CACHEATTR, MISC;
> - raise exceptions on access to unconfigured SRs/invalid access to configured
> SRs;
> - ad
Hi.
This is my current patch queue for xtensa:
- add support for a number of Special Registers: ATOMCTL, CACHEATTR, MISC;
- raise exceptions on access to unconfigured SRs/invalid access to configured
SRs;
- add unit tests for SR access and for s32c1i opcode;
- use movcond to re-implement some opc
