Re: [Qemu-devel] [PATCH-4.2 v1 6/6] target/riscv: Fix Floating Point register names

On Wed, Jul 31, 2019 at 1:10 AM Chih-Min Chao wrote: > > > > On Wed, Jul 31, 2019 at 2:41 AM Alistair Francis wrote: >> >> On Mon, Jul 29, 2019 at 8:19 AM Chih-Min Chao >> wrote: >> > >> > >> > On Fri, Jul 26, 2019 at 2:56 AM Alistair Francis >> > wrote: >> >> >> >> From: Atish Patra >> >> >

Re: [Qemu-devel] [PATCH-4.2 v1 6/6] target/riscv: Fix Floating Point register names

On Wed, Jul 31, 2019 at 2:41 AM Alistair Francis wrote: > On Mon, Jul 29, 2019 at 8:19 AM Chih-Min Chao > wrote: > > > > > > On Fri, Jul 26, 2019 at 2:56 AM Alistair Francis < > alistair.fran...@wdc.com> wrote: > >> > >> From: Atish Patra > >> > >> As per the RISC-V spec, Floating Point registe

Re: [Qemu-devel] [PATCH-4.2 v1 6/6] target/riscv: Fix Floating Point register names

On Mon, Jul 29, 2019 at 8:19 AM Chih-Min Chao wrote: > > > On Fri, Jul 26, 2019 at 2:56 AM Alistair Francis > wrote: >> >> From: Atish Patra >> >> As per the RISC-V spec, Floating Point registers are named as f0..f31 >> so lets fix the register names accordingly. >> >> Signed-off-by: Atish Patr

Re: [Qemu-devel] [PATCH-4.2 v1 6/6] target/riscv: Fix Floating Point register names

On Fri, Jul 26, 2019 at 2:56 AM Alistair Francis wrote: > From: Atish Patra > > As per the RISC-V spec, Floating Point registers are named as f0..f31 > so lets fix the register names accordingly. > > Signed-off-by: Atish Patra > Signed-off-by: Alistair Francis > --- > target/riscv/cpu.c | 8 +

[Qemu-devel] [PATCH-4.2 v1 6/6] target/riscv: Fix Floating Point register names

From: Atish Patra As per the RISC-V spec, Floating Point registers are named as f0..f31 so lets fix the register names accordingly. Signed-off-by: Atish Patra Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tar