On 22/12/2016 13:37, Kirill A. Shutemov wrote:
> On Fri, Dec 16, 2016 at 01:59:36PM +0100, Paolo Bonzini wrote:
>>
>>
>> On 15/12/2016 01:13, Kirill A. Shutemov wrote:
>>> The new paging more is extension of IA32e mode with more additional page
>>> table level.
>>>
>>> It brings support of 57-bit
On Fri, Dec 16, 2016 at 01:59:36PM +0100, Paolo Bonzini wrote:
>
>
> On 15/12/2016 01:13, Kirill A. Shutemov wrote:
> > The new paging more is extension of IA32e mode with more additional page
> > table level.
> >
> > It brings support of 57-bit vitrual address space (128PB) and 52-bit
> > physi
On Thu, Dec 15, 2016 at 03:13:05AM +0300, Kirill A. Shutemov wrote:
> The new paging more is extension of IA32e mode with more additional page
> table level.
>
> It brings support of 57-bit vitrual address space (128PB) and 52-bit
> physical address space (4PB).
>
> The structure of new page tabl
On Fri, Dec 16, 2016 at 01:59:36PM +0100, Paolo Bonzini wrote:
>
>
> On 15/12/2016 01:13, Kirill A. Shutemov wrote:
> > The new paging more is extension of IA32e mode with more additional page
> > table level.
> >
> > It brings support of 57-bit vitrual address space (128PB) and 52-bit
> > physi
On 15/12/2016 01:13, Kirill A. Shutemov wrote:
> The new paging more is extension of IA32e mode with more additional page
> table level.
>
> It brings support of 57-bit vitrual address space (128PB) and 52-bit
> physical address space (4PB).
>
> The structure of new page table level is identica
The new paging more is extension of IA32e mode with more additional page
table level.
It brings support of 57-bit vitrual address space (128PB) and 52-bit
physical address space (4PB).
The structure of new page table level is identical to pml4.
The feature is enumerated with CPUID.(EAX=07H, ECX=
