On Fri, 23 Sep 2016, Richard Henderson wrote:
> While increasing the max per insn is indeed one way to approach this, aarch64
> is being remarkably inefficient in this case. With the following, I see a
> reduction from 387 ops to 261 ops; for a 64-bit host, the reduction is from
> 258 ops to 195
On 09/22/2016 04:53 PM, Joseph Myers wrote:
MAX_OP_PER_INSTR is currently 266, reported in commit
14dcdac82f398cbac874c8579b9583fab31c67bf to be the worst case for the
ARM A64 decoder.
Whether or not it was in fact the worst case at that time in 2014, I'm
observing the instruction 0x4c006020 (st
On Fri, 23 Sep 2016, Laurent Desnogues wrote:
> Hello,
>
> On Fri, Sep 23, 2016 at 1:53 AM, Joseph Myers wrote:
> > MAX_OP_PER_INSTR is currently 266, reported in commit
> > 14dcdac82f398cbac874c8579b9583fab31c67bf to be the worst case for the
> > ARM A64 decoder.
> >
> > Whether or not it was i
Hello,
On Fri, Sep 23, 2016 at 1:53 AM, Joseph Myers wrote:
> MAX_OP_PER_INSTR is currently 266, reported in commit
> 14dcdac82f398cbac874c8579b9583fab31c67bf to be the worst case for the
> ARM A64 decoder.
>
> Whether or not it was in fact the worst case at that time in 2014, I'm
> observing the
MAX_OP_PER_INSTR is currently 266, reported in commit
14dcdac82f398cbac874c8579b9583fab31c67bf to be the worst case for the
ARM A64 decoder.
Whether or not it was in fact the worst case at that time in 2014, I'm
observing the instruction 0x4c006020 (st1 {v0.16b-v2.16b}, [x1])
generate 386 ops from
