On 8/24/18 6:17 AM, Roman Kapl wrote:
> The TCG backend uses LOWREGMASK to get the low 7 bits of register numbers.
> This
> was defined as no-op for 32-bit x86, with the assumption that we have eight
> registers anyway. This assumption is not true once we have xmm regs.
>
> Since LOWREGMASK was a
Hi,
On 09/20/2018 02:19 PM, Philippe Mathieu-Daudé wrote:
On 8/24/18 3:17 PM, Roman Kapl wrote:
The TCG backend uses LOWREGMASK to get the low 7 bits of register numbers. This
7 = 0b111: the low 3 bits?
Yes, low 3 bits, 8 registers, the commit message is wrong.
Thanks, Roman Kapl
On 8/24/18 3:17 PM, Roman Kapl wrote:
> The TCG backend uses LOWREGMASK to get the low 7 bits of register numbers.
> This
7 = 0b111: the low 3 bits?
> was defined as no-op for 32-bit x86, with the assumption that we have eight
> registers anyway. This assumption is not true once we have xmm regs
ping http://patchwork.ozlabs.org/patch/961849/
On 08/24/2018 03:17 PM, Roman Kapl wrote:
The TCG backend uses LOWREGMASK to get the low 7 bits of register numbers. This
was defined as no-op for 32-bit x86, with the assumption that we have eight
registers anyway. This assumption is not true once
The TCG backend uses LOWREGMASK to get the low 7 bits of register numbers. This
was defined as no-op for 32-bit x86, with the assumption that we have eight
registers anyway. This assumption is not true once we have xmm regs.
Since LOWREGMASK was a no-op, xmm register indidices were wrong in opcode
