Re: [Qemu-devel] [PATCH] target-ppc: fixed translation of mcrxr instruction

2014-06-17 Thread Alexander Graf
On 17.06.14 15:26, Tom Musta wrote: On 6/17/2014 12:54 AM, Sorav Bansal wrote: Fixed bug in gen_mcrxr() in target-ppc/translate.c: The XER[SO], XER[OV], and XER[CA] flags are stored in the least significant bit (bit 0) of their respective registers. They need to be shifted left (by their respec

Re: [Qemu-devel] [PATCH] target-ppc: fixed translation of mcrxr instruction

2014-06-17 Thread Tom Musta
On 6/17/2014 12:54 AM, Sorav Bansal wrote: > Fixed bug in gen_mcrxr() in target-ppc/translate.c: > The XER[SO], XER[OV], and XER[CA] flags are stored in the least > significant bit (bit 0) of their respective registers. They need > to be shifted left (by their respective offsets) to generate the fi

[Qemu-devel] [PATCH] target-ppc: fixed translation of mcrxr instruction

2014-06-16 Thread Sorav Bansal
Fixed bug in gen_mcrxr() in target-ppc/translate.c: The XER[SO], XER[OV], and XER[CA] flags are stored in the least significant bit (bit 0) of their respective registers. They need to be shifted left (by their respective offsets) to generate the final XER value. The old translation code for the 'mc