On Tue, Feb 23, 2010 at 11:55:14AM -0800, Nathan Froyd wrote:
> The CRF_{CH,CL,CH_OR_CL,CH_AND_CL} constants were all off by one bit
> position. Because of this, the SPE evcmp* family of instructions would
> store values in the result condition register that were also off by one
> bit position.
>
The CRF_{CH,CL,CH_OR_CL,CH_AND_CL} constants were all off by one bit
position. Because of this, the SPE evcmp* family of instructions would
store values in the result condition register that were also off by one
bit position.
Fixed by using the CRF_{LT,GT,EQ,SO} constants for the shift amounts.
