On Fri, 5 Jun 2015, Leon Alrae wrote:
> > As a side note, I have seen that you have added a check for MIPS2 to the
> > ERET instruction. This is correct, but given in practice we don't
> > emulate any MIPS1 CPU, I do wonder if it's not the time to make MIPS2
> > the basic instruction set and remov
On 05/06/15 10:42, Aurelien Jarno wrote:
> On 2015-06-04 17:00, Leon Alrae wrote:
>> ERETNC is identical to ERET except that an ERETNC will not clear the LLbit
>> that is set by execution of an LL instruction, and thus when placed between
>> an LL and SC sequence, will never cause the SC to fail.
>
On 2015-06-04 17:00, Leon Alrae wrote:
> ERETNC is identical to ERET except that an ERETNC will not clear the LLbit
> that is set by execution of an LL instruction, and thus when placed between
> an LL and SC sequence, will never cause the SC to fail.
>
> Presence of ERETNC is denoted by the Confi
ERETNC is identical to ERET except that an ERETNC will not clear the LLbit
that is set by execution of an LL instruction, and thus when placed between
an LL and SC sequence, will never cause the SC to fail.
Presence of ERETNC is denoted by the Config5.LLB.
Signed-off-by: Leon Alrae
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disas/mi
