On Tue, 2 Dec 2014, Leon Alrae wrote:
> > @@ -19276,6 +19276,10 @@ void mips_cpu_dump_state(CPUState *cs, F
> > env->CP0_Status, env->CP0_Cause, env->CP0_EPC);
> > cpu_fprintf(f, "Config0 0x%08x Config1 0x%08x LLAddr 0x"
> > TARGET_FMT_lx "\n",
> > env->
On 18/11/2014 03:20, Maciej W. Rozycki wrote:
> @@ -19276,6 +19276,10 @@ void mips_cpu_dump_state(CPUState *cs, F
> env->CP0_Status, env->CP0_Cause, env->CP0_EPC);
> cpu_fprintf(f, "Config0 0x%08x Config1 0x%08x LLAddr 0x"
> TARGET_FMT_lx "\n",
> env->CP0
Include CP0.Config2 through CP0.Config5 registers in the register dump
produced with the `info registers' monitor command. Align vertically
with the registers already output.
Signed-off-by: Maciej W. Rozycki
---
Hi,
This proved useful in debugging a CP0.Config3.ISAOnExc problem, fixed
with
