On 02 Jun 2014, at 18:02, Peter Maydell wrote:
> On 30 May 2014 16:15, Fabian Aggeler wrote:
>> Corrected handling of writes to TTBCR for ARMv8 (previously UNK/SBZP
>> bits are not RES0) and ARMv7 (new bits PD0/PD1 for CPUs with Security
>> Extensions). Extracting T0SZ/T1SZ now uses 3 bits in A
On 30 May 2014 16:15, Fabian Aggeler wrote:
> Corrected handling of writes to TTBCR for ARMv8 (previously UNK/SBZP
> bits are not RES0) and ARMv7 (new bits PD0/PD1 for CPUs with Security
> Extensions). Extracting T0SZ/T1SZ now uses 3 bits in Aarch32 and 6 bits
> in Aarch64 as bits [5:3] are now RE
Corrected handling of writes to TTBCR for ARMv8 (previously UNK/SBZP
bits are not RES0) and ARMv7 (new bits PD0/PD1 for CPUs with Security
Extensions). Extracting T0SZ/T1SZ now uses 3 bits in Aarch32 and 6 bits
in Aarch64 as bits [5:3] are now RES0 when writing to Aarch32 TTBCR,
and not guaranteed
