On 10 December 2012 03:32, wrote:
> Fix a bug on the ARM GIC model where interrupts are not
> set pending on the correct target CPUs when they are
> triggered by writes to the Interrupt Set Enable or
> Set Pending registers.
>
> Signed-off-by: Daniel Sangorrin
Reviewed-by: Peter Maydell
Thank
Fix a bug on the ARM GIC model where interrupts are not
set pending on the correct target CPUs when they are
triggered by writes to the Interrupt Set Enable or
Set Pending registers.
Signed-off-by: Daniel Sangorrin
---
hw/arm_gic.c |5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
d
