Re: [Qemu-devel] [PATCH] target-arm: Implement FPEXC32_EL2 system register

2016-01-20 Thread Sergey Fedorov
On 18.01.2016 19:05, Peter Maydell wrote: > Oops, got the qemu-arm email address wrong... > > On 18 January 2016 at 15:53, Peter Maydell wrote: >> The AArch64 FPEXC32_EL2 system register is visible at EL2 and EL3, >> and allows those exception levels to read and write the FPEXC >> register for a l

Re: [Qemu-devel] [PATCH] target-arm: Implement FPEXC32_EL2 system register

2016-01-20 Thread Edgar E. Iglesias
On Mon, Jan 18, 2016 at 04:05:36PM +, Peter Maydell wrote: > Oops, got the qemu-arm email address wrong... Replied to the wrong email before... Reviewed-by: Edgar E. Iglesias > > On 18 January 2016 at 15:53, Peter Maydell wrote: > > The AArch64 FPEXC32_EL2 system register is visible at E

Re: [Qemu-devel] [PATCH] target-arm: Implement FPEXC32_EL2 system register

2016-01-20 Thread Edgar E. Iglesias
On Mon, Jan 18, 2016 at 03:53:34PM +, Peter Maydell wrote: > The AArch64 FPEXC32_EL2 system register is visible at EL2 and EL3, > and allows those exception levels to read and write the FPEXC > register for a lower exception level that is using AArch32. > > Signed-off-by: Peter Maydell Revie

Re: [Qemu-devel] [PATCH] target-arm: Implement FPEXC32_EL2 system register

2016-01-18 Thread Peter Maydell
Oops, got the qemu-arm email address wrong... On 18 January 2016 at 15:53, Peter Maydell wrote: > The AArch64 FPEXC32_EL2 system register is visible at EL2 and EL3, > and allows those exception levels to read and write the FPEXC > register for a lower exception level that is using AArch32. > > Si

[Qemu-devel] [PATCH] target-arm: Implement FPEXC32_EL2 system register

2016-01-18 Thread Peter Maydell
The AArch64 FPEXC32_EL2 system register is visible at EL2 and EL3, and allows those exception levels to read and write the FPEXC register for a lower exception level that is using AArch32. Signed-off-by: Peter Maydell --- ARM Trusted Firmware expects this to exist (as does your average hypervisor