On 11 July 2016 at 19:47, Sergey Sorokin wrote:
[re TLBIALLNSNH and TLBIALLNSNHIS]
> Table G4-25 Effect of the TLB maintenance instructions says:
> b. Available only in an implementation that includes EL2.
>
> So seems they should be in el2_cp_reginfo which is exist regardless EL3
> enabled.
> A
11.07.2016, 21:36, "Peter Maydell" :
> On 11 July 2016 at 19:23, Sergey Sorokin wrote:
>> 11.07.2016, 20:39, "Peter Maydell" :
+
+ CPU_FOREACH(other_cs) {
+ tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E2, -1);
+ }
+}
+
static const
On 11 July 2016 at 19:23, Sergey Sorokin wrote:
> 11.07.2016, 20:39, "Peter Maydell" :
>>> +
>>> + CPU_FOREACH(other_cs) {
>>> + tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E2, -1);
>>> + }
>>> +}
>>> +
>>> static const ARMCPRegInfo cp_reginfo[] = {
>>> /* Define the sec
11.07.2016, 20:39, "Peter Maydell" :
>> +
>> + CPU_FOREACH(other_cs) {
>> + tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E2, -1);
>> + }
>> +}
>> +
>> static const ARMCPRegInfo cp_reginfo[] = {
>> /* Define the secure and non-secure FCSE identifier CP registers
>> *
ping
http://patchwork.ozlabs.org/patch/639688/
