Re: [Qemu-devel] [PATCH] target/riscv: Only flush TLB if SATP.ASID changes

On Wed, 08 May 2019 10:38:35 PDT (-0700), jonat...@fintelia.io wrote: There is an analogous change for ARM here: https://patchwork.kernel.org/patch/10649857 Signed-off-by: Jonathan Behrens --- target/riscv/csr.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/risc

Re: [Qemu-devel] [PATCH] target/riscv: Only flush TLB if SATP.ASID changes

On Wed, May 8, 2019 at 10:39 AM Jonathan Behrens wrote: > > There is an analogous change for ARM here: > https://patchwork.kernel.org/patch/10649857 > > Signed-off-by: Jonathan Behrens Reviewed-by: Alistair Francis Alistair > --- > target/riscv/csr.c | 4 +++- > 1 file changed, 3 insertions(

Re: [Qemu-devel] [PATCH] target/riscv: Only flush TLB if SATP.ASID changes

On 5/8/19 10:38 AM, Jonathan Behrens wrote: > There is an analogous change for ARM here: > https://patchwork.kernel.org/patch/10649857 > > Signed-off-by: Jonathan Behrens > --- > target/riscv/csr.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson r~

[Qemu-devel] [PATCH] target/riscv: Only flush TLB if SATP.ASID changes

There is an analogous change for ARM here: https://patchwork.kernel.org/patch/10649857 Signed-off-by: Jonathan Behrens --- target/riscv/csr.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6083c782a1..1ec1222da1 100644 --- a/t