On 11/2/18 9:48 AM, Peter Maydell wrote:
>> +static inline bool isar_feature_aa64_a32(const ARMISARegisters *id)
>> +{
>> +return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) == 2;
>> +}
>> +
>
> Doesn't the stuff in the Arm ARM's "Principles of the ID
> scheme for fields in ID registers" abo
On 1 November 2018 at 21:57, Richard Henderson
wrote:
> When populating id registers from kvm, on a host that doesn't support
> aarch32 mode at all, aa32_arm_div will not be supported either.
>
> Signed-off-by: Richard Henderson
> ---
>
> "Tested" on an APM Mustang, which does support AArch32. I
Richard Henderson writes:
> When populating id registers from kvm, on a host that doesn't support
> aarch32 mode at all, aa32_arm_div will not be supported either.
>
> Signed-off-by: Richard Henderson
> ---
>
> "Tested" on an APM Mustang, which does support AArch32. I'm not
> sure, off hand,
On 1/11/18 22:57, Richard Henderson wrote:
When populating id registers from kvm, on a host that doesn't support
aarch32 mode at all, aa32_arm_div will not be supported either.
Signed-off-by: Richard Henderson
---
"Tested" on an APM Mustang, which does support AArch32. I'm not
sure, off hand,
When populating id registers from kvm, on a host that doesn't support
aarch32 mode at all, aa32_arm_div will not be supported either.
Signed-off-by: Richard Henderson
---
"Tested" on an APM Mustang, which does support AArch32. I'm not
sure, off hand, which cpu(s) don't have it, and Alex didn't
