On 17 June 2018 at 19:48, Julia Suvorova wrote:
> I can make it if you wish.
> In addition, we can simplify following "if" by removing ARM_FEATURE_V6
> since V7M and V8M define V6:
>
> if (!arm_dc_feature(s, ARM_FEATURE_V7) &&
> !(arm_dc_feature(s, ARM_FEATURE_V6) &&
> arm_dc
On 17.06.2018 19:33, Peter Maydell wrote:
On 17 June 2018 at 06:36, Richard Henderson
wrote:
On 06/15/2018 12:55 AM, Peter Maydell wrote:
+uint32_t armv6m_insn[] = {0xf3808000 /* msr */, 0xf3b08040 /* dsb */,
+ 0xf3b08050 /* dmb */, 0xf3b08060 /* isb */,
+
On 17 June 2018 at 06:36, Richard Henderson
wrote:
> On 06/15/2018 12:55 AM, Peter Maydell wrote:
>>> +uint32_t armv6m_insn[] = {0xf3808000 /* msr */, 0xf3b08040 /* dsb */,
>>> + 0xf3b08050 /* dmb */, 0xf3b08060 /* isb */,
>>> + 0xf3e08
On 06/15/2018 12:55 AM, Peter Maydell wrote:
>> +uint32_t armv6m_insn[] = {0xf3808000 /* msr */, 0xf3b08040 /* dsb */,
>> + 0xf3b08050 /* dmb */, 0xf3b08060 /* isb */,
>> + 0xf3e08000 /* mrs */, 0xf000d000 /* bl */};
>> +uint32_t arm
On 12 June 2018 at 21:46, Julia Suvorova wrote:
> @@ -10085,10 +10091,25 @@ static void disas_thumb2_insn(DisasContext *s,
> uint32_t insn)
> int conds;
> int logic_cc;
>
> -/* The only 32 bit insn that's allowed for Thumb1 is the combined
> - * BL/BLX prefix and suffix.
> +
On 15.06.2018 13:55, Peter Maydell wrote:
On 12 June 2018 at 21:46, Julia Suvorova wrote:
ARMv6-M supports 6 Thumb2 instructions. This patch checks for these
instructions and allows their execution.
Like Thumb2 cores, ARMv6-M always interprets BL instruction as 32-bit.
This patch is required f
On 12 June 2018 at 21:46, Julia Suvorova wrote:
> ARMv6-M supports 6 Thumb2 instructions. This patch checks for these
> instructions and allows their execution.
> Like Thumb2 cores, ARMv6-M always interprets BL instruction as 32-bit.
>
> This patch is required for future Cortex-M0 support.
>
> Sig
On Wed, Jun 13, 2018 at 08:10:23PM +0300, Julia Suvorova via Qemu-devel wrote:
> On 13.06.2018 17:05, Stefan Hajnoczi wrote:
> > On Tue, Jun 12, 2018 at 11:46:32PM +0300, Julia Suvorova wrote:
> > > ARMv6-M supports 6 Thumb2 instructions. This patch checks for these
> > > instructions and allows th
On 13.06.2018 17:05, Stefan Hajnoczi wrote:
On Tue, Jun 12, 2018 at 11:46:32PM +0300, Julia Suvorova wrote:
ARMv6-M supports 6 Thumb2 instructions. This patch checks for these
instructions and allows their execution.
Like Thumb2 cores, ARMv6-M always interprets BL instruction as 32-bit.
This pa
On Tue, Jun 12, 2018 at 11:46:32PM +0300, Julia Suvorova wrote:
> ARMv6-M supports 6 Thumb2 instructions. This patch checks for these
> instructions and allows their execution.
> Like Thumb2 cores, ARMv6-M always interprets BL instruction as 32-bit.
>
> This patch is required for future Cortex-M0
ARMv6-M supports 6 Thumb2 instructions. This patch checks for these
instructions and allows their execution.
Like Thumb2 cores, ARMv6-M always interprets BL instruction as 32-bit.
This patch is required for future Cortex-M0 support.
Signed-off-by: Julia Suvorova
---
target/arm/translate.c | 35
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