On Mon, Mar 05, 2012 at 06:34:51PM +, Blue Swirl wrote:
> On Sun, Mar 4, 2012 at 22:29, Michael S. Tsirkin wrote:
> > On Sun, Mar 04, 2012 at 09:54:02PM +, Blue Swirl wrote:
> >> >> 19.3.1.10 tells that the header type is 0, as you noted too. Still,
> >> >> the register layout matches brid
On Sun, Mar 4, 2012 at 22:29, Michael S. Tsirkin wrote:
> On Sun, Mar 04, 2012 at 09:54:02PM +, Blue Swirl wrote:
>> >> 19.3.1.10 tells that the header type is 0, as you noted too. Still,
>> >> the register layout matches bridge spec instead, for example there are
>> >> bus number registers in
On Sun, Mar 04, 2012 at 09:54:02PM +, Blue Swirl wrote:
> >> 19.3.1.10 tells that the header type is 0, as you noted too. Still,
> >> the register layout matches bridge spec instead, for example there are
> >> bus number registers in place of BAR 2.
> >
> > Sorry I don't see this in 19.3.1
> >
On 04/03/12 19:51, Blue Swirl wrote:
I now know the root cause of the problem. OpenBIOS programs the BARs
somewhat correctly just by accident. The initial io_base and mem_base
for BARs are not correct, but because the host bridge BARs (and also 6
of which 4 are not even BARs!) are programmed fir
On Sun, Mar 4, 2012 at 21:28, Michael S. Tsirkin wrote:
> On Sun, Mar 04, 2012 at 08:32:26PM +, Blue Swirl wrote:
>> On Sun, Mar 4, 2012 at 20:02, Michael S. Tsirkin wrote:
>> > On Sun, Mar 04, 2012 at 07:51:02PM +, Blue Swirl wrote:
>> >> On Sun, Mar 4, 2012 at 17:35, Michael S. Tsirkin
On Sun, Mar 04, 2012 at 08:32:26PM +, Blue Swirl wrote:
> On Sun, Mar 4, 2012 at 20:02, Michael S. Tsirkin wrote:
> > On Sun, Mar 04, 2012 at 07:51:02PM +, Blue Swirl wrote:
> >> On Sun, Mar 4, 2012 at 17:35, Michael S. Tsirkin wrote:
> >> > On Sun, Mar 04, 2012 at 05:07:34PM +, Blue
On Sun, Mar 4, 2012 at 20:02, Michael S. Tsirkin wrote:
> On Sun, Mar 04, 2012 at 07:51:02PM +, Blue Swirl wrote:
>> On Sun, Mar 4, 2012 at 17:35, Michael S. Tsirkin wrote:
>> > On Sun, Mar 04, 2012 at 05:07:34PM +, Blue Swirl wrote:
>> >> On Sun, Mar 4, 2012 at 15:22, Michael S. Tsirkin
On Sun, Mar 04, 2012 at 07:51:02PM +, Blue Swirl wrote:
> On Sun, Mar 4, 2012 at 17:35, Michael S. Tsirkin wrote:
> > On Sun, Mar 04, 2012 at 05:07:34PM +, Blue Swirl wrote:
> >> On Sun, Mar 4, 2012 at 15:22, Michael S. Tsirkin wrote:
> >> > On Sun, Mar 04, 2012 at 02:35:28PM +, Blue
On Sun, Mar 4, 2012 at 17:35, Michael S. Tsirkin wrote:
> On Sun, Mar 04, 2012 at 05:07:34PM +, Blue Swirl wrote:
>> On Sun, Mar 4, 2012 at 15:22, Michael S. Tsirkin wrote:
>> > On Sun, Mar 04, 2012 at 02:35:28PM +, Blue Swirl wrote:
>> >> On Sun, Mar 4, 2012 at 14:23, Michael S. Tsirkin
On Sun, Mar 04, 2012 at 06:11:20PM +, Mark Cave-Ayland wrote:
> On 04/03/12 17:49, Blue Swirl wrote:
>
> >>According to the spec it is a device, so should be ok?
> >>If I just make BAR4 writeable we get past the
> >>bios screen at least.
> >>Maybe openbios gets confused if a device has no BARs
On Sun, Mar 04, 2012 at 06:11:20PM +, Mark Cave-Ayland wrote:
> On 04/03/12 17:49, Blue Swirl wrote:
>
> >>According to the spec it is a device, so should be ok?
> >>If I just make BAR4 writeable we get past the
> >>bios screen at least.
> >>Maybe openbios gets confused if a device has no BARs
On Sun, Mar 04, 2012 at 05:49:04PM +, Blue Swirl wrote:
> On Sun, Mar 4, 2012 at 16:42, Michael S. Tsirkin wrote:
> > On Sun, Mar 04, 2012 at 02:26:13PM +, Blue Swirl wrote:
> >> > It seems to have to do with the host bridge.
> >> > It's unusual to have host bridge present itself
> >> > as
On 04/03/12 17:49, Blue Swirl wrote:
According to the spec it is a device, so should be ok?
If I just make BAR4 writeable we get past the
bios screen at least.
Maybe openbios gets confused if a device has no BARs?
Do things work for you with the patch below?
All it does is make BAR4 writeable, a
On Sun, Mar 4, 2012 at 16:42, Michael S. Tsirkin wrote:
> On Sun, Mar 04, 2012 at 02:26:13PM +, Blue Swirl wrote:
>> > It seems to have to do with the host bridge.
>> > It's unusual to have host bridge present itself
>> > as a pci to pci bridge but there it is.
>>
>> It looks like the I/O base
On Sun, Mar 04, 2012 at 05:07:34PM +, Blue Swirl wrote:
> On Sun, Mar 4, 2012 at 15:22, Michael S. Tsirkin wrote:
> > On Sun, Mar 04, 2012 at 02:35:28PM +, Blue Swirl wrote:
> >> On Sun, Mar 4, 2012 at 14:23, Michael S. Tsirkin wrote:
> >> > On Sun, Mar 04, 2012 at 01:38:38PM +, Blue
On Sun, Mar 4, 2012 at 15:22, Michael S. Tsirkin wrote:
> On Sun, Mar 04, 2012 at 02:35:28PM +, Blue Swirl wrote:
>> On Sun, Mar 4, 2012 at 14:23, Michael S. Tsirkin wrote:
>> > On Sun, Mar 04, 2012 at 01:38:38PM +, Blue Swirl wrote:
>> >> On Sun, Mar 4, 2012 at 13:28, Michael S. Tsirkin
On Sun, Mar 04, 2012 at 02:26:13PM +, Blue Swirl wrote:
> > It seems to have to do with the host bridge.
> > It's unusual to have host bridge present itself
> > as a pci to pci bridge but there it is.
>
> It looks like the I/O base calculations in OpenBIOS are confused
Where's the source for
On Sun, Mar 04, 2012 at 02:35:28PM +, Blue Swirl wrote:
> Yes, it's the host bridge, also known as PBM. It's documented in
> UltraSPARC IIi User's Manual and there it says that the device is
> found in the configuration space.
So it seems I can make things work if
I disable is_bridge and make
On Sun, Mar 04, 2012 at 02:35:28PM +, Blue Swirl wrote:
> On Sun, Mar 4, 2012 at 14:23, Michael S. Tsirkin wrote:
> > On Sun, Mar 04, 2012 at 01:38:38PM +, Blue Swirl wrote:
> >> On Sun, Mar 4, 2012 at 13:28, Michael S. Tsirkin wrote:
> >> > On Sun, Mar 04, 2012 at 12:37:57PM +, Blue
On Sun, Mar 4, 2012 at 14:23, Michael S. Tsirkin wrote:
> On Sun, Mar 04, 2012 at 01:38:38PM +, Blue Swirl wrote:
>> On Sun, Mar 4, 2012 at 13:28, Michael S. Tsirkin wrote:
>> > On Sun, Mar 04, 2012 at 12:37:57PM +, Blue Swirl wrote:
>> >> On Sun, Mar 4, 2012 at 12:21, Michael S. Tsirkin
On Sun, Mar 4, 2012 at 14:08, Michael S. Tsirkin wrote:
> On Sun, Mar 04, 2012 at 01:33:42PM +, Blue Swirl wrote:
>> On Sun, Mar 4, 2012 at 13:22, Michael S. Tsirkin wrote:
>> > On Sun, Mar 04, 2012 at 02:41:33PM +0200, Avi Kivity wrote:
>> >> On 03/04/2012 02:38 PM, Blue Swirl wrote:
>> >> >
On Sun, Mar 04, 2012 at 01:38:38PM +, Blue Swirl wrote:
> On Sun, Mar 4, 2012 at 13:28, Michael S. Tsirkin wrote:
> > On Sun, Mar 04, 2012 at 12:37:57PM +, Blue Swirl wrote:
> >> On Sun, Mar 4, 2012 at 12:21, Michael S. Tsirkin wrote:
> >> > On Sun, Mar 04, 2012 at 10:27:24AM +, Blue
On Sun, Mar 04, 2012 at 01:33:42PM +, Blue Swirl wrote:
> On Sun, Mar 4, 2012 at 13:22, Michael S. Tsirkin wrote:
> > On Sun, Mar 04, 2012 at 02:41:33PM +0200, Avi Kivity wrote:
> >> On 03/04/2012 02:38 PM, Blue Swirl wrote:
> >> > >>
> >> > >> This unassigned memory exception is triggered bec
On Sun, Mar 4, 2012 at 13:28, Michael S. Tsirkin wrote:
> On Sun, Mar 04, 2012 at 12:37:57PM +, Blue Swirl wrote:
>> On Sun, Mar 4, 2012 at 12:21, Michael S. Tsirkin wrote:
>> > On Sun, Mar 04, 2012 at 10:27:24AM +, Blue Swirl wrote:
>> >> On Sun, Mar 4, 2012 at 09:46, Michael S. Tsirkin
On Sun, Mar 04, 2012 at 12:37:57PM +, Blue Swirl wrote:
> On Sun, Mar 4, 2012 at 12:21, Michael S. Tsirkin wrote:
> > On Sun, Mar 04, 2012 at 10:27:24AM +, Blue Swirl wrote:
> >> On Sun, Mar 4, 2012 at 09:46, Michael S. Tsirkin wrote:
> >> > commit 5caef97a16010f818ea8b950e2ee24ba876643ad
On Sun, Mar 4, 2012 at 13:22, Michael S. Tsirkin wrote:
> On Sun, Mar 04, 2012 at 02:41:33PM +0200, Avi Kivity wrote:
>> On 03/04/2012 02:38 PM, Blue Swirl wrote:
>> > >>
>> > >> This unassigned memory exception is triggered because CMD646 IDE I/O
>> > >> registers are not accessible:
>> > >>
>> >
On Sun, Mar 04, 2012 at 12:37:57PM +, Blue Swirl wrote:
> On Sun, Mar 4, 2012 at 12:21, Michael S. Tsirkin wrote:
> > On Sun, Mar 04, 2012 at 10:27:24AM +, Blue Swirl wrote:
> >> On Sun, Mar 4, 2012 at 09:46, Michael S. Tsirkin wrote:
> >> > commit 5caef97a16010f818ea8b950e2ee24ba876643ad
On Sun, Mar 04, 2012 at 02:41:33PM +0200, Avi Kivity wrote:
> On 03/04/2012 02:38 PM, Blue Swirl wrote:
> > >>
> > >> This unassigned memory exception is triggered because CMD646 IDE I/O
> > >> registers are not accessible:
> > >>
> > >> (qemu) info pci
> > >> Bus 0, device 5, function 0:
> >
On Sun, Mar 04, 2012 at 12:46:23PM +, Blue Swirl wrote:
> On Sun, Mar 4, 2012 at 12:41, Avi Kivity wrote:
> > On 03/04/2012 02:38 PM, Blue Swirl wrote:
> >> >>
> >> >> This unassigned memory exception is triggered because CMD646 IDE I/O
> >> >> registers are not accessible:
> >> >>
> >> >> (qe
On Sun, Mar 4, 2012 at 12:41, Avi Kivity wrote:
> On 03/04/2012 02:38 PM, Blue Swirl wrote:
>> >>
>> >> This unassigned memory exception is triggered because CMD646 IDE I/O
>> >> registers are not accessible:
>> >>
>> >> (qemu) info pci
>> >> Bus 0, device 5, function 0:
>> >> IDE control
On Sun, Mar 4, 2012 at 12:33, Michael S. Tsirkin wrote:
> On Sun, Mar 04, 2012 at 10:27:24AM +, Blue Swirl wrote:
>> On Sun, Mar 4, 2012 at 09:46, Michael S. Tsirkin wrote:
>> > commit 5caef97a16010f818ea8b950e2ee24ba876643ad introduced
>> > a regression: we do not make IO base/limit upper 16
On 03/04/2012 02:38 PM, Blue Swirl wrote:
> >>
> >> This unassigned memory exception is triggered because CMD646 IDE I/O
> >> registers are not accessible:
> >>
> >> (qemu) info pci
> >> Bus 0, device 5, function 0:
> >> IDE controller: PCI device 1095:0646
> >> IRQ 1.
> >> BAR
On Sun, Mar 4, 2012 at 12:28, Avi Kivity wrote:
> On 03/04/2012 12:27 PM, Blue Swirl wrote:
>> On Sun, Mar 4, 2012 at 09:46, Michael S. Tsirkin wrote:
>> > commit 5caef97a16010f818ea8b950e2ee24ba876643ad introduced
>> > a regression: we do not make IO base/limit upper 16
>> > bit registers writea
On Sun, Mar 4, 2012 at 12:21, Michael S. Tsirkin wrote:
> On Sun, Mar 04, 2012 at 10:27:24AM +, Blue Swirl wrote:
>> On Sun, Mar 4, 2012 at 09:46, Michael S. Tsirkin wrote:
>> > commit 5caef97a16010f818ea8b950e2ee24ba876643ad introduced
>> > a regression: we do not make IO base/limit upper 16
On 03/04/2012 02:33 PM, Michael S. Tsirkin wrote:
> On Sun, Mar 04, 2012 at 10:27:24AM +, Blue Swirl wrote:
> > On Sun, Mar 4, 2012 at 09:46, Michael S. Tsirkin wrote:
> > > commit 5caef97a16010f818ea8b950e2ee24ba876643ad introduced
> > > a regression: we do not make IO base/limit upper 16
> >
On Sun, Mar 04, 2012 at 02:33:02PM +0200, Michael S. Tsirkin wrote:
> On Sun, Mar 04, 2012 at 10:27:24AM +, Blue Swirl wrote:
> > On Sun, Mar 4, 2012 at 09:46, Michael S. Tsirkin wrote:
> > > commit 5caef97a16010f818ea8b950e2ee24ba876643ad introduced
> > > a regression: we do not make IO base/
On Sun, Mar 04, 2012 at 10:27:24AM +, Blue Swirl wrote:
> On Sun, Mar 4, 2012 at 09:46, Michael S. Tsirkin wrote:
> > commit 5caef97a16010f818ea8b950e2ee24ba876643ad introduced
> > a regression: we do not make IO base/limit upper 16
> > bit registers writeable, so we should report a 16 bit
> >
On 03/04/2012 12:27 PM, Blue Swirl wrote:
> On Sun, Mar 4, 2012 at 09:46, Michael S. Tsirkin wrote:
> > commit 5caef97a16010f818ea8b950e2ee24ba876643ad introduced
> > a regression: we do not make IO base/limit upper 16
> > bit registers writeable, so we should report a 16 bit
> > IO range type, no
On Sun, Mar 04, 2012 at 10:27:24AM +, Blue Swirl wrote:
> On Sun, Mar 4, 2012 at 09:46, Michael S. Tsirkin wrote:
> > commit 5caef97a16010f818ea8b950e2ee24ba876643ad introduced
> > a regression: we do not make IO base/limit upper 16
> > bit registers writeable, so we should report a 16 bit
> >
On Sun, Mar 4, 2012 at 09:46, Michael S. Tsirkin wrote:
> commit 5caef97a16010f818ea8b950e2ee24ba876643ad introduced
> a regression: we do not make IO base/limit upper 16
> bit registers writeable, so we should report a 16 bit
> IO range type, not a 32 bit one.
> Note that PCI_PREF_RANGE_TYPE_32 i
commit 5caef97a16010f818ea8b950e2ee24ba876643ad introduced
a regression: we do not make IO base/limit upper 16
bit registers writeable, so we should report a 16 bit
IO range type, not a 32 bit one.
Note that PCI_PREF_RANGE_TYPE_32 is 0x0, but PCI_IO_RANGE_TYPE_32 is 0x1.
In particular, this broke
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