On 18 July 2018 at 14:59, Julia Suvorova wrote:
> On 17.07.2018 15:58, Peter Maydell wrote:
>>
>> On 10 July 2018 at 16:33, Julia Suvorova wrote:
>>>
>>> The differences from ARMv7-M NVIC are:
>>>* ARMv6-M only supports up to 32 external interrupts
>>> (configurable feature already). The
On 17.07.2018 15:58, Peter Maydell wrote:
On 10 July 2018 at 16:33, Julia Suvorova wrote:
The differences from ARMv7-M NVIC are:
* ARMv6-M only supports up to 32 external interrupts
(configurable feature already). The ICTR is reserved.
* Active Bit Register is reserved.
* ARMv6-M s
On 10 July 2018 at 16:33, Julia Suvorova wrote:
> The differences from ARMv7-M NVIC are:
> * ARMv6-M only supports up to 32 external interrupts
>(configurable feature already). The ICTR is reserved.
> * Active Bit Register is reserved.
> * ARMv6-M supports 4 priority levels against 256 i
On Wed, Jul 11, 2018 at 02:33:14PM +0100, Peter Maydell wrote:
> On 11 July 2018 at 14:25, Stefan Hajnoczi wrote:
> > On Tue, Jul 10, 2018 at 06:33:35PM +0300, Julia Suvorova via Qemu-devel
> > wrote:
> >> The differences from ARMv7-M NVIC are:
> >> * ARMv6-M only supports up to 32 external int
On 11 July 2018 at 14:25, Stefan Hajnoczi wrote:
> On Tue, Jul 10, 2018 at 06:33:35PM +0300, Julia Suvorova via Qemu-devel wrote:
>> The differences from ARMv7-M NVIC are:
>> * ARMv6-M only supports up to 32 external interrupts
>>(configurable feature already). The ICTR is reserved.
>> * A
On Tue, Jul 10, 2018 at 06:33:35PM +0300, Julia Suvorova via Qemu-devel wrote:
> The differences from ARMv7-M NVIC are:
> * ARMv6-M only supports up to 32 external interrupts
>(configurable feature already). The ICTR is reserved.
> * Active Bit Register is reserved.
> * ARMv6-M supports 4
The differences from ARMv7-M NVIC are:
* ARMv6-M only supports up to 32 external interrupts
(configurable feature already). The ICTR is reserved.
* Active Bit Register is reserved.
* ARMv6-M supports 4 priority levels against 256 in ARMv7-M.
Signed-off-by: Julia Suvorova
---
hw/intc/arm
