On Tue, 6 Aug 2019 at 23:12, Eddie James wrote:
>
>
> On 8/5/19 9:31 AM, Peter Maydell wrote:
> > On Wed, 26 Jun 2019 at 19:43, Eddie James wrote:
> >> diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
> >> index 7b80b1d..51a733b 100644
> >> --- a/hw/sd/sdhci.c
> >> +++ b/hw/sd/sdhci.c
> >> @@ -213,7 +
On 8/5/19 9:31 AM, Peter Maydell wrote:
On Wed, 26 Jun 2019 at 19:43, Eddie James wrote:
The Aspeed SOCs have two SD/MMC controllers. Add a device that
encapsulates both of these controllers and models the Aspeed-specific
registers and behavior.
Both controllers use a single HW interrupt. In
On Wed, 26 Jun 2019 at 19:43, Eddie James wrote:
>
> The Aspeed SOCs have two SD/MMC controllers. Add a device that
> encapsulates both of these controllers and models the Aspeed-specific
> registers and behavior.
>
> Both controllers use a single HW interrupt. In order to trigger that
> interrupt
The Aspeed SOCs have two SD/MMC controllers. Add a device that
encapsulates both of these controllers and models the Aspeed-specific
registers and behavior.
Both controllers use a single HW interrupt. In order to trigger that
interrupt, a function pointer was added to the generic SDHCI structure.
