On 23/10/2017 12:16, Gerd Hoffmann wrote:
On Mon, 2017-10-23 at 11:46 +0300, Marcel Apfelbaum wrote:
On 23/10/2017 8:45, Gerd Hoffmann wrote:
Hi,
The guest will still run with 40 bits physical!
(judging the code anyway, I hope I am wrong)
Then, the stakes are not so big, the Guest kernel
On Mon, 2017-10-23 at 11:46 +0300, Marcel Apfelbaum wrote:
> On 23/10/2017 8:45, Gerd Hoffmann wrote:
> > Hi,
> >
> > > The guest will still run with 40 bits physical!
> > > (judging the code anyway, I hope I am wrong)
> > >
> > > Then, the stakes are not so big, the Guest kernel will disregar
On 23/10/2017 8:45, Gerd Hoffmann wrote:
Hi,
The guest will still run with 40 bits physical!
(judging the code anyway, I hope I am wrong)
Then, the stakes are not so big, the Guest kernel will disregard
the 64bit hole since is not CPU addressable and go on.
But then there is no working 64
Hi,
> The guest will still run with 40 bits physical!
> (judging the code anyway, I hope I am wrong)
>
> Then, the stakes are not so big, the Guest kernel will disregard
> the 64bit hole since is not CPU addressable and go on.
But then there is no working 64bit hole for hotplug ...
cheers,
On 20/10/2017 13:59, Gerd Hoffmann wrote:
On Fri, 2017-10-20 at 11:32 +0200, Laszlo Ersek wrote:
On 10/20/17 08:55, Gerd Hoffmann wrote:
Hi,
commit message says:
It turns out that some 32 bit windows guests crash
if 64 bit PCI hole size is >2G.
Why this suddenly isn't a pro
Hi Gerd,
On 20/10/2017 9:55, Gerd Hoffmann wrote:
Hi,
commit message says:
It turns out that some 32 bit windows guests crash
if 64 bit PCI hole size is >2G.
Why this suddenly isn't a problem any more?
I suppose it is, so we need a way to turn it "off".
Or have machine
On Fri, 2017-10-20 at 11:32 +0200, Laszlo Ersek wrote:
> On 10/20/17 08:55, Gerd Hoffmann wrote:
> > Hi,
> >
> > > > commit message says:
> > > >
> > > >
> > > > It turns out that some 32 bit windows guests crash
> > > > if 64 bit PCI hole size is >2G.
> > > >
> > > >
> > > > Why t
On 10/20/17 08:55, Gerd Hoffmann wrote:
> Hi,
>
>>> commit message says:
>>>
>>>
>>> It turns out that some 32 bit windows guests crash
>>> if 64 bit PCI hole size is >2G.
>>>
>>>
>>> Why this suddenly isn't a problem any more?
>>>
>>
>> I suppose it is, so we need a way to turn it "
Hi,
> > commit message says:
> >
> >
> > It turns out that some 32 bit windows guests crash
> > if 64 bit PCI hole size is >2G.
> >
> >
> > Why this suddenly isn't a problem any more?
> >
>
> I suppose it is, so we need a way to turn it "off".
Or have machine types behave differ
On 19/10/2017 16:03, Gerd Hoffmann wrote:
Hi,
- commit 39848901818 pc: limit 64 bit hole to 2G by default
shows us QEMU had the 64bit PCI hole, so it is a regression.
commit message says:
It turns out that some 32 bit windows guests crash
if 64 bit PCI hole size is >2G.
Hi,
> - commit 39848901818 pc: limit 64 bit hole to 2G by default
> shows us QEMU had the 64bit PCI hole, so it is a regression.
commit message says:
It turns out that some 32 bit windows guests crash
if 64 bit PCI hole size is >2G.
Why this suddenly isn't a problem any more?
A
On 10/19/17 13:29, Marcel Apfelbaum wrote:
> Hi Laszlo,
>
> On 19/10/2017 13:41, Laszlo Ersek wrote:
>> On 10/19/17 11:30, Marcel Apfelbaum wrote:
>>>
>>> Hi Laszlo,
>>>
>>> On 18/10/2017 14:40, Laszlo Ersek wrote:
Hi Marcel,
On 10/18/17 11:58, Marcel Apfelbaum wrote:
> Currentl
Hi Laszlo,
On 19/10/2017 13:41, Laszlo Ersek wrote:
On 10/19/17 11:30, Marcel Apfelbaum wrote:
Hi Laszlo,
On 18/10/2017 14:40, Laszlo Ersek wrote:
Hi Marcel,
On 10/18/17 11:58, Marcel Apfelbaum wrote:
Currently there is no MMIO range over 4G
reserved for PCI hotplug. Since the 32bit PCI ho
On 10/19/17 11:30, Marcel Apfelbaum wrote:
>
> Hi Laszlo,
>
> On 18/10/2017 14:40, Laszlo Ersek wrote:
>> Hi Marcel,
>>
>> On 10/18/17 11:58, Marcel Apfelbaum wrote:
>>> Currently there is no MMIO range over 4G
>>> reserved for PCI hotplug. Since the 32bit PCI hole
>>> depends on the number of co
Hi Laszlo,
On 18/10/2017 14:40, Laszlo Ersek wrote:
Hi Marcel,
On 10/18/17 11:58, Marcel Apfelbaum wrote:
Currently there is no MMIO range over 4G
reserved for PCI hotplug. Since the 32bit PCI hole
depends on the number of cold-plugged PCI devices
and other factors, it is very possible is too
Hi Marcel,
On 10/18/17 11:58, Marcel Apfelbaum wrote:
> Currently there is no MMIO range over 4G
> reserved for PCI hotplug. Since the 32bit PCI hole
> depends on the number of cold-plugged PCI devices
> and other factors, it is very possible is too small
> to hotplug PCI devices with large BARs.
Hi Igor,
On 18/10/2017 13:45, Igor Mammedov wrote:
On Wed, 18 Oct 2017 12:58:07 +0300
Marcel Apfelbaum wrote:
Currently there is no MMIO range over 4G
reserved for PCI hotplug. Since the 32bit PCI hole
depends on the number of cold-plugged PCI devices
and other factors, it is very possible is
On Wed, 18 Oct 2017 12:58:07 +0300
Marcel Apfelbaum wrote:
> Currently there is no MMIO range over 4G
> reserved for PCI hotplug. Since the 32bit PCI hole
> depends on the number of cold-plugged PCI devices
> and other factors, it is very possible is too small
> to hotplug PCI devices with large
Currently there is no MMIO range over 4G
reserved for PCI hotplug. Since the 32bit PCI hole
depends on the number of cold-plugged PCI devices
and other factors, it is very possible is too small
to hotplug PCI devices with large BARs.
Fix it by reserving all the address space after
RAM (and the res
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