On 06/26/2018 12:50 PM, G 3 wrote:
>
> If FPSCR[ZE] is set or not set, answer = 0x7ff0. This indicates to
> me that the fdiv instruction needs a little work. This is what I think should
> happen. If division by zero takes place and the FPSCR[ZE] bit is set, then
> the
> value in the
On Jun 26, 2018, at 9:49 AM, Richard Henderson wrote:
On 06/25/2018 03:23 PM, Programmingkid wrote:
On Jun 25, 2018, at 5:08 PM, Richard Henderson
wrote:
On Mon, Jun 25, 2018, 08:23 G 3 wrote:
Try
uint64_t expected_answer = 0xdeadbeef;
...
c.i = expected_answer;
On 06/25/2018 03:23 PM, Programmingkid wrote:
>
>> On Jun 25, 2018, at 5:08 PM, Richard Henderson
>> wrote:
>>
>> On Mon, Jun 25, 2018, 08:23 G 3 wrote:
>>>
>>> Try
>>>
>>> uint64_t expected_answer = 0xdeadbeef;
>>> ...
>>> c.i = expected_answer;
>>> asm volatile("fdiv %
> On Jun 25, 2018, at 5:08 PM, Richard Henderson
> wrote:
>
> On Mon, Jun 25, 2018, 08:23 G 3 wrote:
> >
> > Try
> >
> > uint64_t expected_answer = 0xdeadbeef;
> > ...
> > c.i = expected_answer;
> > asm volatile("fdiv %0, %1, %2" : "+f"(c.d) : "f"(1.0), "f"(0.0));
> >
On Mon, Jun 25, 2018, 08:23 G 3 wrote:
> >
> > Try
> >
> > uint64_t expected_answer = 0xdeadbeef;
> > ...
> > c.i = expected_answer;
> > asm volatile("fdiv %0, %1, %2" : "+f"(c.d) : "f"(1.0), "f"(0.0));
> >
> > to avoid depending on uninitialized data. (This expected valu
On Jun 24, 2018, at 11:47 PM, Richard Henderson wrote:
On 06/24/2018 11:38 AM, Programmingkid wrote:
void test_division_by_zero()
{
Converter c;
uint64_t expected_answer = 0x0;
uint32_t actual_fpscr, expected_fpscr = 0xc410;
reset_fpscr();
set_fpscr_bit(ZE);
asm vo
On 06/24/2018 11:38 AM, Programmingkid wrote:
> void test_division_by_zero()
> {
> Converter c;
> uint64_t expected_answer = 0x0;
> uint32_t actual_fpscr, expected_fpscr = 0xc410;
> reset_fpscr();
> set_fpscr_bit(ZE);
> asm volatile("fdiv %0, %1, %2" : "=f"(c.d) : "f"(1.
On Sun, Jun 24, 2018 at 11:24:17PM -0400, G 3 wrote:
>
> On Jun 24, 2018, at 8:46 PM, David Gibson wrote:
>
> > On Fri, Jun 22, 2018 at 10:22:58PM -0400, John Arbuckle wrote:
> > > When the fdiv instruction divides a finite number by zero,
> > > the result actually depends on the FPSCR[ZE] bit. I
On Jun 24, 2018, at 8:46 PM, David Gibson wrote:
On Fri, Jun 22, 2018 at 10:22:58PM -0400, John Arbuckle wrote:
When the fdiv instruction divides a finite number by zero,
the result actually depends on the FPSCR[ZE] bit. If this
bit is set, the return value is zero. If it is not set
the resul
On Fri, Jun 22, 2018 at 10:22:58PM -0400, John Arbuckle wrote:
> When the fdiv instruction divides a finite number by zero,
> the result actually depends on the FPSCR[ZE] bit. If this
> bit is set, the return value is zero. If it is not set
> the result should be either positive or negative infinit
On Sat, Jun 23, 2018 at 04:17:08PM -0400, Programmingkid wrote:
>
> > On Jun 23, 2018, at 12:17 PM, Richard Henderson
> > wrote:
> >
> > On 06/22/2018 07:22 PM, John Arbuckle wrote:
> >> When the fdiv instruction divides a finite number by zero,
> >> the result actually depends on the FPSCR[ZE]
> On Jun 24, 2018, at 2:30 PM, Richard Henderson
> wrote:
>
> On 06/24/2018 06:46 AM, Programmingkid wrote:
>>> Even in your referenced PDF, table 3-13, it says that frD is unmodified.
>>
>> Actually it says when FPSCR[ZE] is set is when frD is unmodified. When
>> FPSCR[ZE] is not set it frD'
On 06/24/2018 06:46 AM, Programmingkid wrote:
>> Even in your referenced PDF, table 3-13, it says that frD is unmodified.
>
> Actually it says when FPSCR[ZE] is set is when frD is unmodified. When
> FPSCR[ZE] is not set it frD's sign is determined by an XOR of the signs of
> the operands. I have
> On Jun 24, 2018, at 12:18 AM, Richard Henderson
> wrote:
>
> On 06/23/2018 01:17 PM, Programmingkid wrote:
https://www.pdfdrive.net/powerpc-microprocessor-family-the-programming-environments-for-32-e3087633.html
This document has the information on the fdiv. Page 133 has the
On 06/23/2018 01:17 PM, Programmingkid wrote:
>>> https://www.pdfdrive.net/powerpc-microprocessor-family-the-programming-environments-for-32-e3087633.html
>>> This document has the information on the fdiv. Page 133 has the information
>>> on what action is executed when a division by zero situatio
> On Jun 23, 2018, at 12:17 PM, Richard Henderson
> wrote:
>
> On 06/22/2018 07:22 PM, John Arbuckle wrote:
>> When the fdiv instruction divides a finite number by zero,
>> the result actually depends on the FPSCR[ZE] bit. If this
>> bit is set, the return value is zero. If it is not set
>> th
On 06/22/2018 07:22 PM, John Arbuckle wrote:
> When the fdiv instruction divides a finite number by zero,
> the result actually depends on the FPSCR[ZE] bit. If this
> bit is set, the return value is zero. If it is not set
> the result should be either positive or negative infinity.
> The sign of t
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180623022258.22158-1-programmingk...@gmail.com
Subject: [Qemu-devel] [PATCH] fix fdiv instruction
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log
When the fdiv instruction divides a finite number by zero,
the result actually depends on the FPSCR[ZE] bit. If this
bit is set, the return value is zero. If it is not set
the result should be either positive or negative infinity.
The sign of this result would depend on the sign of the
two inputs.
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