On Tue, Sep 24, 2019 at 4:35 PM Alistair Francis wrote:
>
> On Tue, Sep 24, 2019 at 1:04 PM Palmer Dabbelt wrote:
> >
> > On Tue, 24 Sep 2019 11:29:25 PDT (-0700), alistai...@gmail.com wrote:
> > > On Mon, Jun 24, 2019 at 11:21 AM Joel Sing wrote:
> > >>
> > >> On 19-06-17 16:52:44, Richard Hend
On Tue, Sep 24, 2019 at 1:04 PM Palmer Dabbelt wrote:
>
> On Tue, 24 Sep 2019 11:29:25 PDT (-0700), alistai...@gmail.com wrote:
> > On Mon, Jun 24, 2019 at 11:21 AM Joel Sing wrote:
> >>
> >> On 19-06-17 16:52:44, Richard Henderson wrote:
> >> > On 6/16/19 12:19 PM, Joel Sing wrote:
> >> > > +
On Tue, 24 Sep 2019 11:29:25 PDT (-0700), alistai...@gmail.com wrote:
On Mon, Jun 24, 2019 at 11:21 AM Joel Sing wrote:
On 19-06-17 16:52:44, Richard Henderson wrote:
> On 6/16/19 12:19 PM, Joel Sing wrote:
> > +/*
> > + * Clear the load reservation, since an SC must fail if there is
>
On Mon, Jun 24, 2019 at 11:21 AM Joel Sing wrote:
>
> On 19-06-17 16:52:44, Richard Henderson wrote:
> > On 6/16/19 12:19 PM, Joel Sing wrote:
> > > +/*
> > > + * Clear the load reservation, since an SC must fail if there is
> > > + * an SC to any address, in between an LR and SC pair.
On Wed, 26 Jun 2019 01:30:35 PDT (-0700), richard.hender...@linaro.org wrote:
On 6/26/19 10:25 AM, Palmer Dabbelt wrote:
You misunderstand. The code is exactly correct as-is. The alignment check
happens implicitly as a part of the softmmu tlb resolution.
Sorry, I thought you said it wasn't h
On 6/26/19 10:25 AM, Palmer Dabbelt wrote:
>> You misunderstand. The code is exactly correct as-is. The alignment check
>> happens implicitly as a part of the softmmu tlb resolution.
>
> Sorry, I thought you said it wasn't happening for linux-user? If it happens
> for both then we're good.
Oh,
On Wed, 26 Jun 2019 00:48:51 PDT (-0700), richard.hender...@linaro.org wrote:
On 6/26/19 8:07 AM, Palmer Dabbelt wrote:
On Tue, 25 Jun 2019 08:36:28 PDT (-0700), richard.hender...@linaro.org wrote:
On 6/24/19 8:08 PM, Joel Sing wrote:
Regarding the alignment for reservations, the
specification
On 6/26/19 8:07 AM, Palmer Dabbelt wrote:
> On Tue, 25 Jun 2019 08:36:28 PDT (-0700), richard.hender...@linaro.org wrote:
>> On 6/24/19 8:08 PM, Joel Sing wrote:
>>> Regarding the alignment for reservations, the
>>> specification does require this, although I do not recall seeing any
>>> enforcemen
On Tue, 25 Jun 2019 08:39:21 PDT (-0700), richard.hender...@linaro.org wrote:
On 6/24/19 8:08 PM, Joel Sing wrote:
From 8ef31a2ce8ef1cbeee92995a0b2994f480e9bb6d Mon Sep 17 00:00:00 2001
From: Joel Sing
Date: Tue, 25 Jun 2019 02:44:24 +1000
Subject: [PATCH] Clear load reservations on qemu riscv
On Tue, 25 Jun 2019 08:36:28 PDT (-0700), richard.hender...@linaro.org wrote:
On 6/24/19 8:08 PM, Joel Sing wrote:
Regarding the alignment for reservations, the
specification does require this, although I do not recall seeing any enforcement
of this by qemu itself.
Ah, I see it now. Enforceme
On 6/24/19 8:08 PM, Joel Sing wrote:
> From 8ef31a2ce8ef1cbeee92995a0b2994f480e9bb6d Mon Sep 17 00:00:00 2001
> From: Joel Sing
> Date: Tue, 25 Jun 2019 02:44:24 +1000
> Subject: [PATCH] Clear load reservations on qemu riscv target
>
> This prevents a load reservation from being placed in one con
On 6/24/19 8:08 PM, Joel Sing wrote:
> Regarding the alignment for reservations, the
> specification does require this, although I do not recall seeing any
> enforcement
> of this by qemu itself.
Ah, I see it now. Enforcement begins here:
static bool trans_lr_w(DisasContext *ctx, arg_lr_w *a)
{
On 19-06-17 16:52:44, Richard Henderson wrote:
> On 6/16/19 12:19 PM, Joel Sing wrote:
> > +/*
> > + * Clear the load reservation, since an SC must fail if there is
> > + * an SC to any address, in between an LR and SC pair.
> > + */
> > +tcg_gen_movi_tl(load_res, 0);
> > +
> >
On Mon, Jun 17, 2019 at 4:53 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 6/16/19 12:19 PM, Joel Sing wrote:
> > +/*
> > + * Clear the load reservation, since an SC must fail if there is
> > + * an SC to any address, in between an LR and SC pair.
> > + */
> > +
On 6/16/19 12:19 PM, Joel Sing wrote:
> +/*
> + * Clear the load reservation, since an SC must fail if there is
> + * an SC to any address, in between an LR and SC pair.
> + */
> +tcg_gen_movi_tl(load_res, 0);
> +
> gen_set_label(l2);
This clear needs to be moved down belo
Patchew URL: https://patchew.org/QEMU/20190616191900.gh61...@hippo.sing.id.au/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH] atomic failures on qemu-system-riscv64
Type: series
Message-id: 20190616191900.gh61
While working on a Go (www.golang.org) port for riscv, I've run
into issues with atomics (namely LR/SC) on qemu-system-riscv64.
There are several reproducers for this problem including one
using gcc builtin atomics:
https://gist.github.com/4a6f656c/8433032a3f70893a278259f8108aad90
And a version
17 matches
Mail list logo
