On Fri, Jan 08, 2016 at 03:33:00PM +, Will Deacon wrote:
[...]
> > /* EL2 debug */
> > + mrs x0, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer
> > + ubfxx0, x0, #8, #4
> > + cmp x0, #1
> > + b.ne4f // Skip if no PMUv3 pres
Hi Lorenzo,
On Fri, Jan 08, 2016 at 12:54:27PM +, Lorenzo Pieralisi wrote:
> The Performance Monitors extension is an optional feature of the
> AArch64 architecture, therefore, in order to access Performance
> Monitors registers safely, the kernel should detect the PMUv3 unit
> presence throug
On Fri, Jan 08, 2016 at 12:54:27PM +, Lorenzo Pieralisi wrote:
> The Performance Monitors extension is an optional feature of the
> AArch64 architecture, therefore, in order to access Performance
> Monitors registers safely, the kernel should detect the PMUv3 unit
> presence through the ID_AA64
The Performance Monitors extension is an optional feature of the
AArch64 architecture, therefore, in order to access Performance
Monitors registers safely, the kernel should detect the PMUv3 unit
presence through the ID_AA64DFR0_EL1 register PMUVer field before
accessing them.
This patch implement
