On Fri, Dec 31, 2010 at 08:46:02PM +0100, Aurelien Jarno wrote:
> On Thu, Dec 30, 2010 at 05:55:38PM +, Blue Swirl wrote:
> > On Wed, Dec 29, 2010 at 9:27 PM, Aurelien Jarno
> > wrote:
> > > Most of emulated CPU have instructions aligned on 16 or 32 bits, while
> > > on others GCC tries to al
On Thu, Dec 30, 2010 at 05:55:38PM +, Blue Swirl wrote:
> On Wed, Dec 29, 2010 at 9:27 PM, Aurelien Jarno wrote:
> > Most of emulated CPU have instructions aligned on 16 or 32 bits, while
> > on others GCC tries to align the target jump location. This means that
> > 1/2 or 3/4 of tb_phys_hash
On Wed, Dec 29, 2010 at 9:27 PM, Aurelien Jarno wrote:
> Most of emulated CPU have instructions aligned on 16 or 32 bits, while
> on others GCC tries to align the target jump location. This means that
> 1/2 or 3/4 of tb_phys_hash entries are never used.
>
> Update the hash function tb_phys_hash_fu
Most of emulated CPU have instructions aligned on 16 or 32 bits, while
on others GCC tries to align the target jump location. This means that
1/2 or 3/4 of tb_phys_hash entries are never used.
Update the hash function tb_phys_hash_func() to ignore the two lowest
bits of the address. This brings a
