Re: [Qemu-devel] [PATCH] RISC-V: Fix pmpcfg register indexing

2019-06-29 Thread Luke Nelson
On Wed, Feb 13, 2019 at 10:12 AM Palmer Dabbelt wrote: > > On Fri, 08 Feb 2019 10:57:17 PST (-0800), alistai...@gmail.com wrote: > > > > Good catch! > > > > Reviewed-by: Alistair Francis > > Ya, thanks -- that's a somewhat embarrassing bug, as someone else just fixed > one on the line below :).

Re: [Qemu-devel] [PATCH] RISC-V: Fix pmpcfg register indexing

2019-02-13 Thread Palmer Dabbelt
On Fri, 08 Feb 2019 10:57:17 PST (-0800), alistai...@gmail.com wrote: On Wed, Jan 30, 2019 at 2:20 PM Luke Nelson wrote: pmpcfg_csr_{read,write} do not correctly handle accesses to PMP configurations 8 through 15 (CSR pmpcfg2) on RV64. The current code computes the pmpcfg index using: (reg

Re: [Qemu-devel] [PATCH] RISC-V: Fix pmpcfg register indexing

2019-02-08 Thread Alistair Francis
On Wed, Jan 30, 2019 at 2:20 PM Luke Nelson wrote: > > pmpcfg_csr_{read,write} do not correctly handle accesses to PMP > configurations 8 through 15 (CSR pmpcfg2) on RV64. > > The current code computes the pmpcfg index using: > > (reg_index * sizeof(target_ulong)) > > This is incorrect on RV64.

[Qemu-devel] [PATCH] RISC-V: Fix pmpcfg register indexing

2019-01-30 Thread Luke Nelson
pmpcfg_csr_{read,write} do not correctly handle accesses to PMP configurations 8 through 15 (CSR pmpcfg2) on RV64. The current code computes the pmpcfg index using: (reg_index * sizeof(target_ulong)) This is incorrect on RV64. For example, when reg_index is 2 (i.e., pmpcfg2), the computed con