Re: [Qemu-devel] [PATCH] RISC-V: Fix isa string logic bug, use popcount to count bits

On Sat, Mar 10, 2018 at 9:33 AM, Eric Blake wrote: > [resend, this time with proper cc's] > > On 03/09/2018 02:20 PM, Michael Clark wrote: > >> Cc: Palmer Dabbelt >> Cc: Peter Maydell >> Signed-off-by: Michael Clark >> --- >> target/riscv/cpu.c | 2 +- >> 1 file changed, 1 insertion(+), 1 d

Re: [Qemu-devel] [PATCH] RISC-V: Fix isa string logic bug, use popcount to count bits

[resend, this time with proper cc's] On 03/09/2018 02:20 PM, Michael Clark wrote: Cc: Palmer Dabbelt Cc: Peter Maydell Signed-off-by: Michael Clark --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 48518

Re: [Qemu-devel] [PATCH] RISC-V: Fix isa string logic bug, use popcount to count bits

On 03/09/2018 02:20 PM, Michael Clark wrote: Cc: Palmer Dabbelt Cc: Peter Maydell Signed-off-by: Michael Clark --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4851890..f0d6d1d 100644 --- a/target/riscv/

[Qemu-devel] [PATCH] RISC-V: Fix isa string logic bug, use popcount to count bits

Cc: Palmer Dabbelt Cc: Peter Maydell Signed-off-by: Michael Clark --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4851890..f0d6d1d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -391,7 +391,7 @