On Wed, May 08, 2013 at 12:34:26PM +0200, Torbjorn Granlund wrote:
> Aurelien Jarno writes:
>
> You have to declare the L bit as invalid, so that trying to execute a
> 64-bit cmp* instruction on a 32-bit CPU causes an invalid instruction
> exception.
>
> Don't people read what I write?
>
On 08.05.2013, at 12:34, Torbjorn Granlund wrote:
> Aurelien Jarno writes:
>
> You have to declare the L bit as invalid, so that trying to execute a
> 64-bit cmp* instruction on a 32-bit CPU causes an invalid instruction
> exception.
>
> Don't people read what I write?
At least on my e500m
Aurelien Jarno writes:
You have to declare the L bit as invalid, so that trying to execute a
64-bit cmp* instruction on a 32-bit CPU causes an invalid instruction
exception.
Don't people read what I write?
I give up.
Goodbye.
--
Torbjörn
On 08.05.2013, at 12:29, Aurelien Jarno wrote:
> On Wed, May 08, 2013 at 12:06:52PM +0200, Alexander Graf wrote:
>> When running a 32bit target CPU with qemu-(system-)-ppc, NARROW_MODE
>> is not set, so we never get to leverage the "32bit only" code path in
>> the compare op handlers.
>>
>> Intr
On Wed, May 08, 2013 at 12:06:52PM +0200, Alexander Graf wrote:
> When running a 32bit target CPU with qemu-(system-)-ppc, NARROW_MODE
> is not set, so we never get to leverage the "32bit only" code path in
> the compare op handlers.
>
> Introduce new handlers based on the 32bit only flag. That wa
When running a 32bit target CPU with qemu-(system-)-ppc, NARROW_MODE
is not set, so we never get to leverage the "32bit only" code path in
the compare op handlers.
Introduce new handlers based on the 32bit only flag. That way we can
have 2 separate functions for 32bit mode and 64bit mode, which ca
