Sorry, I have sent wrong patch.
A
By the way, the second version of the patch was sent already.
I have sentA the second version of the patch.
Some architectures (e.g. ARMv8) need the address which is aligned
to a size more than the size of the memory access.
It's enougth the current costless alignment check implementation in QEMU,
but we need to support the alignment size specifying.
Signed-off-by: Sergey Sorokin
---
include/exec/cpu-
On 06/20/2016 10:33 AM, Sergey Sorokin wrote:
I'm thinking of the AVR target currently under review which requires
TARGET_PAGE_BITS == 8 in order to support the memory device layout.
What is maximum alignment size for AVR? I think it's possible to implement some
checks for this maximum.
It's
A
A
20.06.2016, 18:45, "Richard Henderson" :
On 06/20/2016 06:56 AM, Sergey Sorokin wrote:
A A /* Flags stored in the low bits of the TLB virtual address.
These are
A - defined so that fast path ram access is all zeros. */
A + * defined so that fast path ram ac
On 06/20/2016 06:56 AM, Sergey Sorokin wrote:
/* Flags stored in the low bits of the TLB virtual address. These are
- defined so that fast path ram access is all zeros. */
+ * defined so that fast path ram access is all zeros.
+ * They start after address alignment bits.
+ */
+#define TLB_FL
Some architectures (e.g. ARMv8) need the address which is aligned
to a size more than the size of the memory access.
It's enougth the current costless alignment check implementation in QEMU,
but we need to support the alignment size specifying.
Signed-off-by: Sergey Sorokin
---
include/exec/cpu-
