Re: [Qemu-devel] [PATCH][MIPS] Per-CPU instruction decoding implementation

Aurelien Jarno wrote: > Hi all, > > The patch below implements per-cpu decoding on the MIPS target. The > supported instruction set is defined by a set of flags. It assumes that > MIPS2 instructions are always supported. It also removes the check for > CP0C0_AT when setting MIPS_HFLAG_64 as it i

[Qemu-devel] [PATCH][MIPS] Per-CPU instruction decoding implementation

Hi all, The patch below implements per-cpu decoding on the MIPS target. The supported instruction set is defined by a set of flags. It assumes that MIPS2 instructions are always supported. It also removes the check for CP0C0_AT when setting MIPS_HFLAG_64 as it is now obsolete. Cheers, Aurelien