[PULL 00/50] riscv-to-apply queue

2025-01-16 Thread Alistair Francis
The following changes since commit 4d5d933bbc7cc52f6cc6b9021f91fa06266222d5: Merge tag 'pull-xenfv-20250116' of git://git.infradead.org/users/dwmw2/qemu into staging (2025-01-16 09:03:43 -0500) are available in the Git repository at: https://github.com/alistair23/qemu.git tags/pull-riscv-to

Re: [PULL 00/50] riscv-to-apply queue

2024-11-05 Thread Alistair Francis
On Tue, Nov 5, 2024 at 5:45 PM Michael Tokarev wrote: > > 05.11.2024 01:57, Alistair Francis wrote: > > >>> RISC-V PR for 9.2 > >>> > >>> * Fix an access to VXSAT > >>> * Expose RV32 cpu to RV64 QEMU > >>> * Don't clear PLIC pending bits on IRQ lowering > >>> * Make PLIC zeroth priority register r

Re: [PULL 00/50] riscv-to-apply queue

2024-11-05 Thread Michael Tokarev
05.11.2024 01:57, Alistair Francis wrote: RISC-V PR for 9.2 * Fix an access to VXSAT * Expose RV32 cpu to RV64 QEMU * Don't clear PLIC pending bits on IRQ lowering * Make PLIC zeroth priority register read-only * Set vtype.vill on CPU reset * Check and update APLIC pending when write sourcecfg

Re: [PULL 00/50] riscv-to-apply queue

2024-11-04 Thread Michael Tokarev
05.11.2024 10:45, Michael Tokarev wrote: target/riscv/csr.c: Fix an access to VXSAT hw/intc: Don't clear pending bits on IRQ lowering target/riscv: Set vtype.vill on CPU reset hw/intc/riscv_aplic: Check and update pending when write sourcecfg target/riscv/kvm: set 'aia_mode' to default in error

Re: [PULL 00/50] riscv-to-apply queue

2024-11-04 Thread Alistair Francis
On Fri, Nov 1, 2024 at 11:40 PM Michael Tokarev wrote: > > 31.10.2024 06:52, Alistair Francis wrote: > > > > > RISC-V PR for 9.2 > > > > * Fix an access to VXSAT > > * Expose RV32 cpu to RV64 QEMU > > * Don't clear PLIC pending bits

Re: [PULL 00/50] riscv-to-apply queue

2024-11-04 Thread Daniel Henrique Barboza
On 11/1/24 10:39 AM, Michael Tokarev wrote: 31.10.2024 06:52, Alistair Francis wrote: RISC-V PR for 9.2 * Fix an access to VXSAT * Expose RV32 cpu to RV64 QEMU * Don't clear PLIC pending bits on IRQ lowering * Make PLIC zeroth

Re: [PULL 00/50] riscv-to-apply queue

2024-11-01 Thread Michael Tokarev
31.10.2024 06:52, Alistair Francis wrote: RISC-V PR for 9.2 * Fix an access to VXSAT * Expose RV32 cpu to RV64 QEMU * Don't clear PLIC pending bits on IRQ lowering * Make PLIC zeroth priority register read-only * Set vtype.vill on

Re: [PULL 00/50] riscv-to-apply queue

2024-11-01 Thread Peter Maydell
On Thu, 31 Oct 2024 at 03:54, Alistair Francis wrote: > > The following changes since commit 58d49b5895f2e0b5cfe4b2901bf24f3320b74f29: > > Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into > staging (2024-10-29 14:00:43 +) > > are available in the Git repository at: > >

[PULL 00/50] riscv-to-apply queue

2024-10-30 Thread Alistair Francis
The following changes since commit 58d49b5895f2e0b5cfe4b2901bf24f3320b74f29: Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into staging (2024-10-29 14:00:43 +) are available in the Git repository at: https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-2024