On 6/7/20 7:39 PM, LIU Zhiwei wrote:
> Maybe I should only gen_set_rm(ctx, 7) for each vector float insn.
> And the csr write method for frm or fcsr will not change.
>
> So I will remove this patch in the next patch set.
Sounds perfect, thanks.
r~
On 2020/6/5 11:30, Richard Henderson wrote:
On 6/4/20 7:50 PM, LIU Zhiwei wrote:
So no scalar insns will require changes within a translation block.
Not true -- scalar insns can encode rm into the instruction.
I think there is a error in gen_set_rm
static void gen_set_rm(DisasContext *ctx
On 6/4/20 7:50 PM, LIU Zhiwei wrote:
> So no scalar insns will require changes within a translation block.
Not true -- scalar insns can encode rm into the instruction.
> I think there is a error in gen_set_rm
>
> static void gen_set_rm(DisasContext *ctx, int rm)
> {
> TCGv_i32 t0;
>
> i
On 2020/6/5 4:15, Richard Henderson wrote:
On 6/2/20 10:46 PM, LIU Zhiwei wrote:
I think you are right. Maybe I should transmit frm to ctx->frm, and check
ctx->frm in vector fp ops.
We can set ctx->frm = env->frm instead of ctx->frm = -1 in
riscv_tr_init_disas_context.
And remove the sente
On 6/2/20 10:46 PM, LIU Zhiwei wrote:
> I think you are right. Maybe I should transmit frm to ctx->frm, and check
> ctx->frm in vector fp ops.
>
> We can set ctx->frm = env->frm instead of ctx->frm = -1 in
> riscv_tr_init_disas_context.
> And remove the sentence ctx->frm = rm; from gen_set_rm.
>
On 2020/6/3 12:27, Richard Henderson wrote:
On 5/21/20 2:43 AM, LIU Zhiwei wrote:
@@ -174,6 +175,9 @@ static int write_frm(CPURISCVState *env, int csrno,
target_ulong val)
env->mstatus |= MSTATUS_FS;
#endif
env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
+if (!riscv_cpu_set_roun
On 5/21/20 2:43 AM, LIU Zhiwei wrote:
> @@ -174,6 +175,9 @@ static int write_frm(CPURISCVState *env, int csrno,
> target_ulong val)
> env->mstatus |= MSTATUS_FS;
> #endif
> env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
> +if (!riscv_cpu_set_rounding_mode(env, env->frm)) {
> +re
On Thu, May 21, 2020 at 3:45 AM LIU Zhiwei wrote:
>
> For scalar float instruction, round mode is encoded in instruction,
> so fp_status is updating dynamiclly.
>
> For vector float instruction, round mode is always frm, so
> update fp_status when frm changes is enough.
>
> Signed-off-by: LIU Zhiw
For scalar float instruction, round mode is encoded in instruction,
so fp_status is updating dynamiclly.
For vector float instruction, round mode is always frm, so
update fp_status when frm changes is enough.
Signed-off-by: LIU Zhiwei
---
target/riscv/csr.c| 7 +++
target/riscv/fpu
