Re: [PATCH v8 2/5] target/riscv: Handle Smrnmi interrupt and exception

2024-11-21 Thread Frank Chang
On Wed, Nov 20, 2024 at 11:29 AM Frank Chang wrote: > On Mon, Nov 18, 2024 at 11:13 AM Alistair Francis > wrote: > >> On Mon, Oct 21, 2024 at 1:06 PM wrote: >> > >> > From: Tommy Wu >> > >> > Because the RNMI interrupt trap handler address is implementation >> defined. >> > We add the 'rnmi-in

Re: [PATCH v8 2/5] target/riscv: Handle Smrnmi interrupt and exception

2024-11-19 Thread Frank Chang
On Mon, Nov 18, 2024 at 11:13 AM Alistair Francis wrote: > On Mon, Oct 21, 2024 at 1:06 PM wrote: > > > > From: Tommy Wu > > > > Because the RNMI interrupt trap handler address is implementation > defined. > > We add the 'rnmi-interrupt-vector' and 'rnmi-exception-vector' as the > property > >

Re: [PATCH v8 2/5] target/riscv: Handle Smrnmi interrupt and exception

2024-11-17 Thread Alistair Francis
On Mon, Oct 21, 2024 at 1:06 PM wrote: > > From: Tommy Wu > > Because the RNMI interrupt trap handler address is implementation defined. > We add the 'rnmi-interrupt-vector' and 'rnmi-exception-vector' as the property > of the harts. It’s very easy for users to set the address based on their > ex

[PATCH v8 2/5] target/riscv: Handle Smrnmi interrupt and exception

2024-10-20 Thread frank . chang
From: Tommy Wu Because the RNMI interrupt trap handler address is implementation defined. We add the 'rnmi-interrupt-vector' and 'rnmi-exception-vector' as the property of the harts. It’s very easy for users to set the address based on their expectation. This patch also adds the functionality to