Re: [PATCH v8 04/17] target/riscv: additional code information for sw check

On Mon, Aug 26, 2024 at 09:59:55AM +1000, Richard Henderson wrote: On 8/24/24 05:01, Deepak Gupta wrote: diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 12484ca7d2..9f08a67a9e 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1761,6 +1761,8 @@ vo

Re: [PATCH v8 04/17] target/riscv: additional code information for sw check

On 8/24/24 05:01, Deepak Gupta wrote: diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 12484ca7d2..9f08a67a9e 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1761,6 +1761,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) cs->watchp

[PATCH v8 04/17] target/riscv: additional code information for sw check

sw check exception support was recently added. This patch further augments sw check exception by providing support for additional code which is provided in *tval. Adds `sw_check_code` field in cpuarchstate. Whenever sw check exception is raised *tval gets the value deposited in `sw_check_code`. Si