On 2024/7/24 23:01, Andrew Jones wrote:
On Sat, Jul 20, 2024 at 07:11:48AM GMT, LIU Zhiwei wrote:
We may need 32-bit max or 32-bit any CPU for RV64 QEMU. Thus we add
these two CPUs for RV64 QEMU.
The reason we don't expose them to RV32 QEMU is that we already have
max or any cpu with the same
On Sat, 20 Jul 2024 at 00:18, LIU Zhiwei wrote:
>
> We may need 32-bit max or 32-bit any CPU for RV64 QEMU. Thus we add
> these two CPUs for RV64 QEMU.
>
> The reason we don't expose them to RV32 QEMU is that we already have
> max or any cpu with the same configuration. Another reason is that
> we
On Sat, Jul 20, 2024 at 07:11:48AM GMT, LIU Zhiwei wrote:
> We may need 32-bit max or 32-bit any CPU for RV64 QEMU. Thus we add
> these two CPUs for RV64 QEMU.
>
> The reason we don't expose them to RV32 QEMU is that we already have
> max or any cpu with the same configuration. Another reason is t
On 7/19/24 8:11 PM, LIU Zhiwei wrote:
We may need 32-bit max or 32-bit any CPU for RV64 QEMU. Thus we add
these two CPUs for RV64 QEMU.
The reason we don't expose them to RV32 QEMU is that we already have
max or any cpu with the same configuration. Another reason is that
we want to follow the
We may need 32-bit max or 32-bit any CPU for RV64 QEMU. Thus we add
these two CPUs for RV64 QEMU.
The reason we don't expose them to RV32 QEMU is that we already have
max or any cpu with the same configuration. Another reason is that
we want to follow the RISC-V custom where addw instruction doesn