On 2020/3/29 0:13, LIU Zhiwei wrote:
On 2020/3/28 23:47, Richard Henderson wrote:
On 3/28/20 8:17 AM, LIU Zhiwei wrote:
Missed the improvement here. See tcg_gen_mulsu2_i64.
Though I have not gotten the principle, the code in
tcg_gen_mulsu2_i64 is much
tidier.
Let A = signed operand,
On 2020/3/28 23:47, Richard Henderson wrote:
On 3/28/20 8:17 AM, LIU Zhiwei wrote:
Missed the improvement here. See tcg_gen_mulsu2_i64.
Though I have not gotten the principle, the code in tcg_gen_mulsu2_i64 is much
tidier.
Let A = signed operand,
B = unsigned operand
P = unsigned
On 3/28/20 8:17 AM, LIU Zhiwei wrote:
>> Missed the improvement here. See tcg_gen_mulsu2_i64.
> Though I have not gotten the principle, the code in tcg_gen_mulsu2_i64 is much
> tidier.
Let A = signed operand,
B = unsigned operand
P = unsigned product
If the sign bit A is set, then P is t
On 2020/3/28 8:06, Richard Henderson wrote:
On 3/17/20 8:06 AM, LIU Zhiwei wrote:
+static int64_t do_mulhsu_d(int64_t s2, uint64_t s1)
+{
+uint64_t hi_64, lo_64, abs_s2 = s2;
+
+if (s2 < 0) {
+abs_s2 = -s2;
+}
+mulu64(&lo_64, &hi_64, abs_s2, s1);
+if (s2 < 0) {
+
On 3/17/20 8:06 AM, LIU Zhiwei wrote:
> +static int64_t do_mulhsu_d(int64_t s2, uint64_t s1)
> +{
> +uint64_t hi_64, lo_64, abs_s2 = s2;
> +
> +if (s2 < 0) {
> +abs_s2 = -s2;
> +}
> +mulu64(&lo_64, &hi_64, abs_s2, s1);
> +if (s2 < 0) {
> +lo_64 = ~lo_64;
> +
On Tue, Mar 17, 2020 at 8:43 AM LIU Zhiwei wrote:
>
> Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/helper.h | 33 +
> target/riscv/insn32.decode | 8 ++
> target/riscv/insn_trans/trans_rvv.inc.c | 10 ++
> target
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 33 +
target/riscv/insn32.decode | 8 ++
target/riscv/insn_trans/trans_rvv.inc.c | 10 ++
target/riscv/vector_helper.c| 156
4 files changed, 207 insertions(+)
diff -
