Re: [PATCH v6 0/7] target/riscv: Add support for Control Transfer Records Ext.

On Mon, Feb 10, 2025 at 4:11 AM Alistair Francis wrote: > > On Thu, Feb 6, 2025 at 9:45 PM Rajnesh Kanwal wrote: > > > > On Thu, Feb 6, 2025 at 5:39 AM Alistair Francis > > wrote: > > > > > > On Wed, Feb 5, 2025 at 9:21 PM Rajnesh Kanwal > > > wrote: > > > > > > > > This series enables Contro

Re: [PATCH v6 0/7] target/riscv: Add support for Control Transfer Records Ext.

On Thu, Feb 6, 2025 at 9:45 PM Rajnesh Kanwal wrote: > > On Thu, Feb 6, 2025 at 5:39 AM Alistair Francis wrote: > > > > On Wed, Feb 5, 2025 at 9:21 PM Rajnesh Kanwal wrote: > > > > > > This series enables Control Transfer Records extension support on riscv > > > platform. This extension is simil

Re: [PATCH v6 0/7] target/riscv: Add support for Control Transfer Records Ext.

On Thu, Feb 6, 2025 at 5:39 AM Alistair Francis wrote: > > On Wed, Feb 5, 2025 at 9:21 PM Rajnesh Kanwal wrote: > > > > This series enables Control Transfer Records extension support on riscv > > platform. This extension is similar to Arch LBR in x86 and BRBE in ARM. > > The Extension has been ra

Re: [PATCH v6 0/7] target/riscv: Add support for Control Transfer Records Ext.

On Wed, Feb 5, 2025 at 9:21 PM Rajnesh Kanwal wrote: > > This series enables Control Transfer Records extension support on riscv > platform. This extension is similar to Arch LBR in x86 and BRBE in ARM. > The Extension has been ratified and this series is based on v1.0 [0] > > CTR extension depend

[PATCH v6 0/7] target/riscv: Add support for Control Transfer Records Ext.

This series enables Control Transfer Records extension support on riscv platform. This extension is similar to Arch LBR in x86 and BRBE in ARM. The Extension has been ratified and this series is based on v1.0 [0] CTR extension depends on both the implementation of S-mode and Sscsrind extension v1.