On 3/16/20 11:01 PM, LIU Zhiwei wrote:
> Two questions here. I don't find the answer in the specification.
>
> 1. Should I check RVF if the instruction uses float register, such as all
> float point instructions and some other instructions?
I would think so, but even the 0.8 spec isn't clear.
On 2020/3/15 12:39, Richard Henderson wrote:
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 9 +
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.inc.c | 47 +
t
On 3/14/20 11:13 PM, LIU Zhiwei wrote:
>> SEW == MO_8 should raise illegal instruction exception.
> I agree. But I didn't find a reference in Section 17.3 both in v0.7.1 and
> v0.8.
>
> Perhaps I should refer
>
> "If the current SEW does not correspond to a supported IEEE floating-point
> type,
On 2020/3/15 12:39, Richard Henderson wrote:
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 9 +
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.inc.c | 47 +
t
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> Signed-off-by: LIU Zhiwei
> ---
> target/riscv/helper.h | 9 +
> target/riscv/insn32.decode | 2 ++
> target/riscv/insn_trans/trans_rvv.inc.c | 47 +
> target/riscv/vector_helper.c| 36
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 9 +
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.inc.c | 47 +
target/riscv/vector_helper.c| 36 +++
4 files changed, 94 insertio
