On 3/14/20 10:15 PM, LIU Zhiwei wrote:
>
>
> On 2020/3/15 10:53, Richard Henderson wrote:
>> On 3/12/20 7:58 AM, LIU Zhiwei wrote:
>>> +static bool trans_vext_x_v(DisasContext *s, arg_r *a)
>>> +{
>>> + if (vext_check_isa_ill(s, RVV)) {
>>> + TCGv_ptr src2;
>>> + TCGv dest, src1;
On 2020/3/15 10:53, Richard Henderson wrote:
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
+static bool trans_vext_x_v(DisasContext *s, arg_r *a)
+{
+if (vext_check_isa_ill(s, RVV)) {
+TCGv_ptr src2;
+TCGv dest, src1;
+gen_helper_vext_x_v fns[4] = {
+gen_helper
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> +static bool trans_vext_x_v(DisasContext *s, arg_r *a)
> +{
> +if (vext_check_isa_ill(s, RVV)) {
> +TCGv_ptr src2;
> +TCGv dest, src1;
> +gen_helper_vext_x_v fns[4] = {
> +gen_helper_vext_x_v_b, gen_helper_vext_x_v_h,
>
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 5
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 33 +
target/riscv/vector_helper.c| 20 +++
4 files changed, 59 insertions(+)
